/*
  tspi_4fx_det.c
  David Rowe 21 June 2006
 
  Linux device driver for Blackfin that implements unit tests
  for the Blackfin-SPI-SiLabs interface.  

  Tests detection of Si labs chips integrated with the 4fx
  SPI decode logic.

  Test expects a FXS module in Port 1 and FXO module in Port 2.
*/

/*
  Copyright (C) 2006 David Rowe
 
  This program is free software; you can redistribute it and/or modify
  it under the terms of the GNU General Public License as published by
  the Free Software Foundation; either version 2 of the License, or
  (at your option) any later version.
  
  This program is distributed in the hope that it will be useful,
  but WITHOUT ANY WARRANTY; without even the implied warranty of
  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  GNU General Public License for more details.
  
  You should have received a copy of the GNU General Public License
  along with this program; if not, write to the Free Software
  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 
*/

#include <linux/module.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/bfin5xx_spi.h>
#include <linux/delay.h>
#include <bfsi.h>

/* 
   Need to do include bfsi module this way due to kbuild restrictions.
   I would rather have it as seperately compiled module but I
   couldn't work out how to specify the path I wanted
*/
#include "../../src/bfsi.c" 

#define BIT_RESET   4 /* GPIO bit tied to nRESET on Si chips */
#define SPI_NCSA    3
#define SPI_NCSB    2

#include "../../src/fx.c" 

/*----------------------- TEST PARAMETERS -----------------------------*/

static int baud      = 4; /* gives max for sys clock = 100 MHz for Si3050 */
static int verbose   = 0;
static int tests     = 100;
static int readtest  = 100;

/*-------------------------- SPORT FUNCTIONS ---------------------------*/

/* 
   Simple SPORT config for this test - we just want an 8kHz FS
   (generated by the Rx side of the SPORT) to feed to the SiLab chips
   FSYNC pin.  SiLabs chip won't reset properly without this signal.
*/

#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
static void sport0_init(void)
{
  printk("sport0_init\n");

  /* ensure serial ports disabled before modifying           */
  bfin_write_SPORT0_TCR1(bfin_read_SPORT0_TCR1() & ~TSPEN);
  bfin_write_SPORT0_RCR1(bfin_read_SPORT0_RCR1() & ~RSPEN);

  /* set up 8kHz FSYNC using rx FS pin and external clock    */
  bfin_write_SPORT0_RFSDIV(255);  /* 8 kHz FSYNC with 2.048MHz PCLK  */

  /* 8 bit word length, external tx clk and tx FS            */
  bfin_write_SPORT0_TCR2(7);     
  bfin_write_SPORT0_TCR1(0);     

  /* 8 bit word length, internal frame sync                  */
  bfin_write_SPORT0_RCR2(7);      /* 8 bit word length       */
  bfin_write_SPORT0_RCR1(IRFS | RFSR);

  /* enable sport0 Tx and Rx */
  bfin_write_SPORT0_TCR1(bfin_read_SPORT0_TCR1() | TSPEN);
  bfin_write_SPORT0_RCR1(bfin_read_SPORT0_RCR1() | RSPEN);
}
#endif

#if defined(CONFIG_BF537)
static void sport1_init(void)
{
  printk("sport1_init\n");

  /* BF537 specific pin muxing configuration */
  bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PGTE|PGRE|PGSE);
  __builtin_bfin_ssync();
  bfin_write_PORTG_FER(bfin_read_PORTG_FER() | 0xFF00);
  __builtin_bfin_ssync();

  /* ensure serial ports disabled before modifying           */
  bfin_write_SPORT1_TCR1(bfin_read_SPORT1_TCR1() & ~TSPEN);
  bfin_write_SPORT1_RCR1(bfin_read_SPORT1_RCR1() & ~RSPEN);

  /* set up 8kHz FSYNC using rx FS pin and external clock    */
  bfin_write_SPORT1_RFSDIV(255);  /* 8 kHz FSYNC with 2.048MHz PCLK  */

  /* 8 bit word length, external tx clk and tx FS            */
  bfin_write_SPORT1_TCR2(7);     
  bfin_write_SPORT1_TCR1(0);     

  /* 8 bit word length, internal frame sync                  */
  bfin_write_SPORT1_RCR2(7);      /* 8 bit word length       */
  bfin_write_SPORT1_RCR1(IRFS | RFSR);

  /* enable sport1 Tx and Rx */
  bfin_write_SPORT1_TCR1(bfin_read_SPORT1_TCR1() | TSPEN);
  bfin_write_SPORT1_RCR1(bfin_read_SPORT1_RCR1() | RSPEN);
}
#endif

/*------------------------ TEST FUNCTION --------------------------*/

void static test(char port_type[]) {
  int i, j, passed, passes;
  u8  reg;

  bfsi_reset(BIT_RESET);
  passed = 1;
  passes = 0;
  for(i=0; i<tests && passed; i++) {

    for(j=0; j<FX_MAX_PORTS; j++) {

      if (port_type[j] == 'O') {

        reg = fx_read_fxo(j+1);
        if (verbose) {
          printk("FXO: 0x%02x\n", reg);
        }
        if (reg == 0x3)
          passes++;
	else {
	  printk("FAILED!\n");
	  printk("test: %d reg: 0x%02x\n", i, reg);
	  passed = 0;
	}
      }
      
      if (port_type[j] == 'S') {

	reg = fx_read_fxs(j+1);
	if (verbose) {
	  printk("FXS: 0x%02x\n", reg);
	}
	if (reg == 0x5)
	  passes++;
	else {
	  printk("FAILED!\n");
	  printk("test: %d reg: 0x%02x\n", i, reg);
	  passed = 0;
	}
      }
    }
  }

  if (passed) {
    printk("baud: 0x%04x tests: %d passes: %d \n", 
	   baud, tests, passes);
    printk("PASSED!\n");
  }
}

/*------------------------MODULE INIT FUNCTION --------------------------*/

static int __init tspi_init_module (void) {
  int  i;
  char port_type[FX_MAX_PORTS];
  u8   reg;

  printk("initializing module\n");
		
  /* init SPI here to ensure that the SPI nCS pin on the SiLabs
     chip is H when the chip is RESET.  This is required to
     configure the chip for SPI/PCM mode. */
  bfsi_spi_init(baud, (1<<SPI_NCSA) | (1<<SPI_NCSB));

  /* we need PCLK and FSYNC applied before device reset */

#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
  sport0_init();
#elif defined(CONFIG_BF537)
  sport1_init();
#endif

  /* optional Si labs read test of port 1 (assumes FXO) */

  if (readtest) {
    bfsi_reset(BIT_RESET);
    for(i=0; i<tests; i++) {
        reg = fx_read_fxo(1);    
	if (verbose) {
	  printk("[%d] fxo reg: 0x%02x\n", i, reg);
	}
    }
  }

  /* try to autodetect each port type */
  fx_auto_detect(port_type, BIT_RESET);

  for(i=0; i<FX_MAX_PORTS; i++) {
    printk("port: %d port_type: %c\n", i+1, port_type[i]);
  }

  /* now test auto detected ports */
  test(port_type);

  return 0;
}

/*------------------------ MODULE CLEANUP FUNCTION -----------------------*/

static void __exit tspi_cleanup_module (void) {
	printk("cleaning up module\n");
	
	/* disable serial port */

#if (defined(CONFIG_BF533) || defined(CONFIG_BF532))
	bfin_write_SPORT0_TCR1(bfin_read_SPORT0_TCR1() & ~TSPEN);
	bfin_write_SPORT0_RCR1(bfin_read_SPORT0_RCR1() & ~RSPEN);
#elif defined(CONFIG_BF537)
	bfin_write_SPORT1_TCR1(bfin_read_SPORT1_TCR1() & ~TSPEN);
	bfin_write_SPORT1_RCR1(bfin_read_SPORT1_RCR1() & ~RSPEN);
#endif

}

module_init(tspi_init_module);
module_exit(tspi_cleanup_module);

MODULE_AUTHOR("David Rowe");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Blackfin/SiLabs 3050 Unit Test");

module_param(baud, int, 0600);
module_param(verbose, int, 0600);
module_param(tests, int, 0600);
module_param(readtest, int, 0600);