--- uClinux-dist-orig/linux-2.6.x/arch/blackfin/Kconfig 2007-04-05 07:37:03.000000000 +0930 +++ uClinux-dist/linux-2.6.x/arch/blackfin/Kconfig 2008-03-10 06:54:18.000000000 +1030 @@ -245,10 +245,35 @@ depends on (BFIN561_BLUETECHNIX_CM) default y +config MEM_MT48LC32M16A2TG_75 + bool "32Mx16 MT48LC32M16A2TG_75" + help + refresh period 64mS, 8192 row addresses, CAS Latency 3, 10 col addresses + config BFIN_SHARED_FLASH_ENET bool depends on (BFIN533_STAMP) - default y + default n + +comment "Hardware addresses" + +config BF1_NET1 + hex "DM9000 eth0 hardware address" + default 0x20100000 + help + Base address of DM9000A Ethernet chip used for eth0 + +config BF1_NET2 + hex "DM9000 eth1 hardware address" + default 0x20200000 + help + Base address of DM9000A Ethernet chip used for eth1 + +config BF1_USB + hex "ISP1362 address" + default 0x20300000 + help + Base address of ISP1362 USB controller source "arch/blackfin/mach-bf533/Kconfig" source "arch/blackfin/mach-bf561/Kconfig" --- uClinux-dist-orig/linux-2.6.x/arch/blackfin/mach-bf533/boards/bf1.c 1970-01-01 09:30:00.000000000 +0930 +++ uClinux-dist/linux-2.6.x/arch/blackfin/mach-bf533/boards/bf1.c 2008-03-10 06:54:18.000000000 +1030 @@ -0,0 +1,288 @@ +/* + * File: arch/blackfin/mach-bf533/bf1.c + * Based on: arch/blackfin/mach-bf533/stamp.c + * Author: Ivan Danov + * + * Created: 2006 + * Description: Board Info File for the BlackfinOne boards + * + * Rev: $Id: bf1.c,v 1.1 2006/10/23 09:54:16 danov Exp $ + * + * Modified: + * Copyright 2006 Intratrade Ltd. + * Copyright 2005 National ICT Australia (NICTA) + * Copyright 2004-2006 Analog Devices Inc. + * + * Bugs: Enter bugs at http://blackfin.uclinux.org/projects/bf1 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see the file COPYING, or write + * to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +#include +#endif +#include +#include + +/* + * Name the Board for the /proc/cpuinfo + */ +#if defined (CONFIG_BFIN533_STAMP) +char *bfin_board_name = "IP04/IP08"; +#else +#error Unknown board +#endif + +/* + * Driver needs to know address, irq and flag pin. + */ +#if defined (CONFIG_BFIN533_STAMP) +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) + +#include + +static struct resource dm9000_resource1[] = { + [0] = { + .start = CONFIG_BF1_NET1, + .end = CONFIG_BF1_NET1 + 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = CONFIG_BF1_NET1 + 2, + .end = CONFIG_BF1_NET1 + 3, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = IRQ_PF15, + .end = IRQ_PF15, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE + } +}; + +static struct resource dm9000_resource2[] = { + [0] = { + .start = CONFIG_BF1_NET2, + .end = CONFIG_BF1_NET2 + 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = CONFIG_BF1_NET2 + 2, + .end = CONFIG_BF1_NET2 + 3, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = IRQ_PF14, + .end = IRQ_PF14, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE + } +}; + +/* +* for the moment we limit ourselves to 16bit IO until some +* better IO routines can be written and tested +*/ +static struct dm9000_plat_data dm9000_platdata1 = { + .flags = DM9000_PLATF_16BITONLY, +}; + +static struct platform_device dm9000_device1 = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(dm9000_resource1), + .resource = dm9000_resource1, + .dev = { + .platform_data = &dm9000_platdata1, + } +}; + +static struct dm9000_plat_data dm9000_platdata2 = { + .flags = DM9000_PLATF_16BITONLY, +}; + +static struct platform_device dm9000_device2 = { + .name = "dm9000", + .id = 1, + .num_resources = ARRAY_SIZE(dm9000_resource2), + .resource = dm9000_resource2, + .dev = { + .platform_data = &dm9000_platdata2, + } +}; + +#endif +#endif // #if defined (CONFIG_BLACKFIN_ONE_V2) + + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) +/* all SPI peripherals info goes here */ + +#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) +static struct bfin5xx_spi_chip spi_mmc_chip_info = { +//CPOL (Clock Polarity) +// 0 - Active high SCK +// 1 - Active low SCK +// CPHA (Clock Phase) Selects transfer format and operation mode +// 0 - SCLK toggles from middle of the first data bit, slave select +// pins controlled by hardware. +// 1 - SCLK toggles from beginning of first data bit, slave select +// pins controller by user software. +// .ctl_reg = 0x1c00, // CPOL=1,CPHA=1,Sandisk 1G work +//NO NO .ctl_reg = 0x1800, // CPOL=1,CPHA=0 +//NO NO .ctl_reg = 0x1400, // CPOL=0,CPHA=1 + .ctl_reg = 0x1000, // CPOL=0,CPHA=0,Sandisk 1G work + .enable_dma = 0, // if 1 - block!!! + .bits_per_word = 8, + .cs_change_per_word = 0, +}; +#endif + +/* Notice: for blackfin, the speed_hz is the value of register + * SPI_BAUD, not the real baudrate */ +static struct spi_board_info bfin_spi_board_info[] __initdata = { +#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) + { + .modalias = "spi_mmc", + .max_speed_hz = 2, + .bus_num = 1, + .chip_select = CONFIG_SPI_MMC_CS_CHAN, + .platform_data = NULL, + .controller_data = &spi_mmc_chip_info, + }, +#endif +}; + +/* SPI controller data */ +static struct bfin5xx_spi_master spi_bfin_master_info = { + .num_chipselect = 8, + .enable_dma = 1, /* master has the ability to do dma transfer */ +}; + +static struct platform_device spi_bfin_master_device = { + .name = "bfin-spi-master", + .id = 1, /* Bus number */ + .dev = { + .platform_data = &spi_bfin_master_info, /* Passed to driver */ + }, +}; +#endif /* spi master and devices */ + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) +static struct resource bfin_uart_resources[] = { + { + .start = 0xFFC00400, + .end = 0xFFC004FF, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bfin_uart_device = { + .name = "bfin-uart", + .id = 1, + .num_resources = ARRAY_SIZE(bfin_uart_resources), + .resource = bfin_uart_resources, +}; +#endif + +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) +static struct resource isp1362_hcd_resources[] = { + { + .start = CONFIG_BF1_USB, + .end = CONFIG_BF1_USB + 1, + .flags = IORESOURCE_MEM, + },{ + .start = CONFIG_BF1_USB + 2, + .end = CONFIG_BF1_USB + 3, + .flags = IORESOURCE_MEM, + },{ + .start = IRQ_PF11, + .end = IRQ_PF11, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + }, +}; + +static struct isp1362_platform_data isp1362_priv = { + .sel15Kres = 1, + .clknotstop = 0, + .oc_enable = 0, // external OC + .int_act_high = 0, + .int_edge_triggered = 0, + .remote_wakeup_connected = 0, + .no_power_switching = 1, + .power_switching_mode = 0, +}; + +static struct platform_device isp1362_hcd_device = { + .name = "isp1362-hcd", + .id = 0, + .dev = { + .platform_data = &isp1362_priv, + }, + .num_resources = ARRAY_SIZE(isp1362_hcd_resources), + .resource = isp1362_hcd_resources, +}; +#endif + + +static struct platform_device *bf1_devices[] __initdata = { +#if defined (CONFIG_BFIN533_STAMP) +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) + &dm9000_device1, + &dm9000_device2, +#endif +#endif + +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + &spi_bfin_master_device, +#endif + +#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) + &bfin_uart_device, +#endif +#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) + &isp1362_hcd_device, +#endif +}; + +static int __init bf1_init(void) +{ + u_int i, j; + + printk(KERN_INFO "%s(): chip_id=%08lX,dspid=%08X\n", + __FUNCTION__, + *((volatile unsigned long *)CHIPID), + bfin_read_DSPID()); + + printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); + platform_add_devices(bf1_devices, ARRAY_SIZE(bf1_devices)); +#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) + for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); i ++) { + j = 1 << bfin_spi_board_info [i]. chip_select; + // set spi cs to 1 + bfin_write_FIO_DIR (bfin_read_FIO_DIR() | j); + bfin_write_FIO_FLAG_S (j); + } + spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); +#endif + return 0; +} + +arch_initcall(bf1_init); --- uClinux-dist-orig/linux-2.6.x/include/asm-blackfin/mach-bf533/mem_init.h 2006-09-26 08:47:45.000000000 +0930 +++ uClinux-dist/linux-2.6.x/include/asm-blackfin/mach-bf533/mem_init.h 2008-03-10 06:54:18.000000000 +1030 @@ -29,7 +29,15 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD) +#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || + CONFIG_MEM_MT48LC16M16A2TG_7E || + CONFIG_MEM_MT48LC8M16A2TG_75 || + CONFIG_MEM_MT48LC8M16A2TG_7E || + CONFIG_MEM_MT48LC32M16A2TG_75 || + CONFIG_MEM_MT48LC32M16A2TG_7E || + CONFIG_MEM_MT48LC64M4A2FB_7E || + CONFIG_MEM_GENERIC_BOARD) + #if (CONFIG_SCLK_HZ > 119402985) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -118,6 +126,13 @@ #define SDRAM_CL CL_3 #endif +#if (CONFIG_MEM_MT48LC32M16A2TG_75) + /*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + #if (CONFIG_MEM_GENERIC_BOARD) /*SDRAM INFORMATION: Modify this for your board */ #define SDRAM_Tref 64 /* Refresh period in milliseconds */ --- uClinux-dist-orig/linux-2.6.x/arch/blackfin/mach-bf533/boards/Makefile 2006-07-29 15:06:15.000000000 +0930 +++ uClinux-dist/linux-2.6.x/arch/blackfin/mach-bf533/boards/Makefile 2008-03-10 06:54:18.000000000 +1030 @@ -3,6 +3,6 @@ # obj-$(CONFIG_GENERIC_BOARD) += generic_board.o -obj-$(CONFIG_BFIN533_STAMP) += stamp.o +obj-$(CONFIG_BFIN533_STAMP) += bf1.o obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o obj-$(CONFIG_BFIN533_BLUETECHNIX_CM) += cm_bf533.o --- uClinux-dist-orig/linux-2.6.x/drivers/mtd/nand/bfin_nand.c 2007-02-07 04:11:48.000000000 +1030 +++ uClinux-dist/linux-2.6.x/drivers/mtd/nand/bfin_nand.c 2008-03-10 06:54:18.000000000 +1030 @@ -56,21 +56,13 @@ { .name = "linux kernel", .offset = 0, - .size = 4 *1024*1024, + .size = 0x800000, }, -#ifdef CONFIG_PNAV10 /* 1G x 8 NAND Flash */ { .name = "file system", - .offset = 4 *1024*1024, - .size = (1024-4) *1024*1024, + .offset = 0x800000, + .size = (CONFIG_BFIN_NAND_SIZE-0x800000), } -#else - { - .name = "file system", - .offset = 4 *1024*1024, - .size = (128-4) *1024*1024, - } -#endif }; /* --- uClinux-dist-orig/linux-2.6.x/drivers/mtd/nand/Kconfig 2007-01-11 22:43:09.000000000 +1030 +++ uClinux-dist/linux-2.6.x/drivers/mtd/nand/Kconfig 2008-03-10 06:54:18.000000000 +1030 @@ -41,10 +41,20 @@ config BFIN_NAND_BASE hex "NAND Flash Base Address" depends on MTD_NAND_BFIN - default 0x20212000 + default 0x20000000 help NAND Flash Base Address +config BFIN_NAND_SIZE + hex "NAND Flash Size" + depends on MTD_NAND_BFIN + default 0x10000000 + help + NAND Flash size, for example 0x10000000 for 256Mbyte, or + 0x02000000 for 32MByte. The NAND will be divided into + two partitions. The first partition is 8M (kernel), the + second partition the remaining space (e.g. yaffs). + config BFIN_NAND_CLE int "NAND Flash Command Latch Enable (CLE) Address strobe A[x]" depends on MTD_NAND_BFIN @@ -67,7 +77,7 @@ range 0 15 if (BF533 || BF532 || BF531) range 0 47 if (BF534 || BF536 || BF537) range 0 47 if BF561 - default 3 + default 10 help NAND Flash Ready Strobe PF[x] --- uClinux-dist-orig/linux-2.6.x/drivers/net/dm9000.c 2007-07-10 15:00:06.000000000 +0930 +++ uClinux-dist/linux-2.6.x/drivers/net/dm9000.c 2008-03-10 06:54:18.000000000 +1030 @@ -395,6 +395,32 @@ } } +static inline unsigned char str2hexnum(unsigned char c) +{ + if(c >= '0' && c <= '9') + return c - '0'; + if(c >= 'a' && c <= 'f') + return c - 'a' + 10; + if(c >= 'A' && c <= 'F') + return c - 'A' + 10; + return 0; /* foo */ +} + +static inline void str2eaddr(unsigned char *ea, unsigned char *str) +{ + int i; + + for(i = 0; i < 6; i++) { + unsigned char num; + + if((*str == '.') || (*str == ':')) + str++; + num = str2hexnum(*str++) << 4; + num |= (str2hexnum(*str++)); + ea[i] = num; + } +} + #define res_size(_r) (((_r)->end - (_r)->start) + 1) /* @@ -411,6 +437,9 @@ int iosize; int i; u32 id_val; + char *pmac; + char ethaddr[6]; + char s[30]; /* Init network device */ ndev = alloc_etherdev(sizeof (struct board_info)); @@ -588,6 +617,18 @@ for (i = 0; i < 6; i++) ndev->dev_addr[i] = db->srom[i]; + /* Check the command line argument */ + if (pdev-> id) + sprintf (s, "ethaddr%i", pdev-> id); + else + strcpy (s, "ethaddr"); + if (((pmac = strstr(saved_command_line, s)) != NULL) && + ((pmac = strstr(pmac, "=")) != NULL)) { + + str2eaddr(ethaddr, pmac + 1); + memcpy(ndev->dev_addr, ethaddr, 6); + } + if (!is_valid_ether_addr(ndev->dev_addr)) { /* try reading from mac */ --- uClinux-dist-orig/linux-2.6.x/drivers/serial/bfin_5xx.c 2007-06-12 11:40:15.000000000 +0930 +++ uClinux-dist/linux-2.6.x/drivers/serial/bfin_5xx.c 2008-03-10 07:50:32.000000000 +1030 @@ -968,7 +968,7 @@ bfin_serial_console_setup(struct console *co, char *options) { struct bfin_serial_port *uart; - int baud = 57600; + int baud = 115200; int bits = 8; int parity = 'n'; #ifdef CONFIG_SERIAL_BFIN_CTSRTS --- uClinux-dist-orig/linux-2.6.x/arch/blackfin/mm/blackfin_sram.c 2007-06-06 10:20:44.000000000 +0930 +++ uClinux-dist/linux-2.6.x/arch/blackfin/mm/blackfin_sram.c 2008-03-18 14:28:54.000000000 +1030 @@ -132,6 +132,8 @@ l1_inst_sram[0].paddr = (void*)L1_CODE_START + (_etext_l1 - _stext_l1); l1_inst_sram[0].size = L1_CODE_LENGTH - (_etext_l1 - _stext_l1); l1_inst_sram[0].flag = SRAM_SLT_FREE; + printk(KERN_INFO "Blackfin Instruction SRAM size: %d Bytes\n", + l1_inst_sram[0].size); #endif /* mutex initialize */ @@ -396,7 +398,7 @@ void *l1_inst_sram_alloc(size_t size) { -#if L1_DATA_A_LENGTH != 0 +#if L1_CODE_LENGTH != 0 unsigned flags; void *addr;