v 20061020 1
C 69500 65000 0 0 0 title-bordered-C.sym
C 82400 67500 1 0 0 bf-gnd-1.sym
C 79200 77100 1 270 0 bf-gnd-1.sym
C 78250 76850 1 270 0 bf-resistor-1.sym
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V 74700 69700 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 69300 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 69500 74400 69400 3 0 0 0 -1 -1
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L 74700 69100 74400 69000 3 0 0 0 -1 -1
V 74700 68900 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 68500 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 68700 74400 68600 3 0 0 0 -1 -1
V 74700 68500 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 68100 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 68300 74400 68200 3 0 0 0 -1 -1
V 74700 68100 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 67700 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 67900 74400 67800 3 0 0 0 -1 -1
V 74700 67700 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 67300 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 67500 74400 67400 3 0 0 0 -1 -1
V 74700 67300 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 66900 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 67100 74400 67000 3 0 0 0 -1 -1
V 74700 66900 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 66500 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 66700 74400 66600 3 0 0 0 -1 -1
V 74700 66500 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 74400 66100 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 74700 66300 74400 66200 3 0 0 0 -1 -1
V 74700 66100 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 74350 71150 8 10 0 1 0 0 1
refdes=J102
T 74700 73900 8 10 0 0 0 0 1
footprint=dheader_13x2_100_mils
T 74700 74100 8 10 0 0 0 0 1
numslots=0
T 74700 74300 8 10 0 0 0 0 1
device=header26
]
{
T 74550 71550 5 10 1 1 0 0 1
refdes=J102
T 74600 71300 5 10 1 1 0 0 1
description=AD2
T 74300 66000 5 10 0 0 0 0 1
footprint=HD_13x2
}
N 70750 69900 72400 69900 4
{
T 71638 69903 5 10 1 1 0 6 1
netname=RESET
}
C 71950 71000 1 90 0 EMBEDDEDgnd-1.sym
[
P 71850 71100 71650 71100 1 0 1
{
T 71789 71158 5 4 0 1 90 0 1
pinnumber=1
T 71789 71158 5 4 0 0 90 0 1
pinseq=1
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L 71850 71000 71850 71200 3 0 0 0 -1 -1
L 71900 71055 71900 71145 3 0 0 0 -1 -1
L 71940 71080 71940 71120 3 0 0 0 -1 -1
T 71900 71300 8 10 0 0 90 0 1
net=GND:1
]
N 70750 71100 71650 71100 4
N 78050 71300 79500 71300 4
{
T 78500 71300 5 10 1 1 0 0 1
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}
N 78050 71500 79500 71500 4
{
T 78500 71500 5 10 1 1 0 0 1
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}
N 78050 71700 79500 71700 4
{
T 78500 71700 5 10 1 1 0 0 1
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}
N 78050 71900 79500 71900 4
{
T 78500 71900 5 10 1 1 0 0 1
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}
N 78050 72100 79500 72100 4
{
T 78500 72100 5 10 1 1 0 0 1
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}
N 78050 72300 79500 72300 4
{
T 78500 72300 5 10 1 1 0 0 1
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N 70750 67700 72400 67700 4
{
T 71357 67714 5 10 1 1 0 6 1
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}
N 70750 67500 72400 67500 4
{
T 71417 67514 5 10 1 1 0 6 1
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}
N 70750 67300 72400 67300 4
{
T 71387 67314 5 10 1 1 0 6 1
netname=BA3
}
N 70750 67100 72400 67100 4
{
T 71417 67114 5 10 1 1 0 6 1
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}
N 70750 66900 72400 66900 4
{
T 71387 66924 5 10 1 1 0 6 1
netname=BA5
}
N 70750 66700 72400 66700 4
{
T 71417 66714 5 10 1 1 0 6 1
netname=BA6
}
N 70750 66500 72400 66500 4
{
T 71392 66514 5 10 1 1 0 6 1
netname=BA7
}
C 72400 67700 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 67700 72500 67800 1 0 0
{
T 72900 67700 5 8 0 0 90 2 1
pinseq=1
T 73000 67700 5 8 0 0 90 2 1
pinnumber=1
T 73100 67700 5 8 0 0 90 2 1
pintype=pas
T 73200 67700 5 8 0 0 90 2 1
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}
L 72600 67900 72500 67800 10 30 0 0 -1 -1
T 72800 67700 5 8 0 0 90 2 1
device=none
T 72700 67700 5 8 0 0 90 2 1
graphical=1
]
C 72400 67500 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 67500 72500 67600 1 0 0
{
T 72900 67500 5 8 0 0 90 2 1
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T 73000 67500 5 8 0 0 90 2 1
pinnumber=1
T 73100 67500 5 8 0 0 90 2 1
pintype=pas
T 73200 67500 5 8 0 0 90 2 1
pinlabel=netside
}
L 72600 67700 72500 67600 10 30 0 0 -1 -1
T 72800 67500 5 8 0 0 90 2 1
device=none
T 72700 67500 5 8 0 0 90 2 1
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]
C 72400 67300 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 67300 72500 67400 1 0 0
{
T 72900 67300 5 8 0 0 90 2 1
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T 73000 67300 5 8 0 0 90 2 1
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T 73100 67300 5 8 0 0 90 2 1
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T 73200 67300 5 8 0 0 90 2 1
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L 72600 67500 72500 67400 10 30 0 0 -1 -1
T 72800 67300 5 8 0 0 90 2 1
device=none
T 72700 67300 5 8 0 0 90 2 1
graphical=1
]
C 72400 67100 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 67100 72500 67200 1 0 0
{
T 72900 67100 5 8 0 0 90 2 1
pinseq=1
T 73000 67100 5 8 0 0 90 2 1
pinnumber=1
T 73100 67100 5 8 0 0 90 2 1
pintype=pas
T 73200 67100 5 8 0 0 90 2 1
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}
L 72600 67300 72500 67200 10 30 0 0 -1 -1
T 72800 67100 5 8 0 0 90 2 1
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T 72700 67100 5 8 0 0 90 2 1
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C 72400 66900 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 66900 72500 67000 1 0 0
{
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T 73100 66900 5 8 0 0 90 2 1
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L 72600 67100 72500 67000 10 30 0 0 -1 -1
T 72800 66900 5 8 0 0 90 2 1
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T 72700 66900 5 8 0 0 90 2 1
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C 72400 66700 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 66700 72500 66800 1 0 0
{
T 72900 66700 5 8 0 0 90 2 1
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T 73000 66700 5 8 0 0 90 2 1
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T 73100 66700 5 8 0 0 90 2 1
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T 73200 66700 5 8 0 0 90 2 1
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L 72600 66900 72500 66800 10 30 0 0 -1 -1
T 72800 66700 5 8 0 0 90 2 1
device=none
T 72700 66700 5 8 0 0 90 2 1
graphical=1
]
C 72400 66500 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 66500 72500 66600 1 0 0
{
T 72900 66500 5 8 0 0 90 2 1
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T 73000 66500 5 8 0 0 90 2 1
pinnumber=1
T 73100 66500 5 8 0 0 90 2 1
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L 72600 66700 72500 66600 10 30 0 0 -1 -1
T 72800 66500 5 8 0 0 90 2 1
device=none
T 72700 66500 5 8 0 0 90 2 1
graphical=1
]
C 72400 68700 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 68700 72500 68800 1 0 0
{
T 72900 68700 5 8 0 0 90 2 1
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T 73000 68700 5 8 0 0 90 2 1
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T 73100 68700 5 8 0 0 90 2 1
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T 73200 68700 5 8 0 0 90 2 1
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L 72600 68900 72500 68800 10 30 0 0 -1 -1
T 72800 68700 5 8 0 0 90 2 1
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T 72700 68700 5 8 0 0 90 2 1
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C 72400 68500 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 68500 72500 68600 1 0 0
{
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T 73000 68500 5 8 0 0 90 2 1
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T 73100 68500 5 8 0 0 90 2 1
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T 73200 68500 5 8 0 0 90 2 1
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L 72600 68700 72500 68600 10 30 0 0 -1 -1
T 72800 68500 5 8 0 0 90 2 1
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T 72700 68500 5 8 0 0 90 2 1
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]
C 78050 74600 1 90 0 EMBEDDEDbusripper-1.sym
[
P 78050 74600 77950 74700 1 0 0
{
T 77550 74600 5 8 0 0 90 0 1
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T 77450 74600 5 8 0 0 90 0 1
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T 77350 74600 5 8 0 0 90 0 1
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T 77250 74600 5 8 0 0 90 0 1
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L 77850 74800 77950 74700 10 30 0 0 -1 -1
T 77650 74600 5 8 0 0 90 0 1
device=none
T 77750 74600 5 8 0 0 90 0 1
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C 78050 74900 1 90 0 EMBEDDEDbusripper-1.sym
[
P 78050 74900 77950 75000 1 0 0
{
T 77550 74900 5 8 0 0 90 0 1
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T 77450 74900 5 8 0 0 90 0 1
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T 77350 74900 5 8 0 0 90 0 1
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T 77250 74900 5 8 0 0 90 0 1
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L 77850 75100 77950 75000 10 30 0 0 -1 -1
T 77650 74900 5 8 0 0 90 0 1
device=none
T 77750 74900 5 8 0 0 90 0 1
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]
C 72400 69900 1 270 0 EMBEDDEDbusripper-1.sym
[
P 72400 69900 72500 70000 1 0 0
{
T 72900 69900 5 8 0 0 90 2 1
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T 73000 69900 5 8 0 0 90 2 1
pinnumber=1
T 73100 69900 5 8 0 0 90 2 1
pintype=pas
T 73200 69900 5 8 0 0 90 2 1
pinlabel=netside
}
L 72600 70100 72500 70000 10 30 0 0 -1 -1
T 72800 69900 5 8 0 0 90 2 1
device=none
T 72700 69900 5 8 0 0 90 2 1
graphical=1
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C 78050 75500 1 90 0 EMBEDDEDbusripper-1.sym
[
P 78050 75500 77950 75600 1 0 0
{
T 77550 75500 5 8 0 0 90 0 1
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T 77450 75500 5 8 0 0 90 0 1
pinnumber=1
T 77350 75500 5 8 0 0 90 0 1
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T 77250 75500 5 8 0 0 90 0 1
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L 77850 75700 77950 75600 10 30 0 0 -1 -1
T 77650 75500 5 8 0 0 90 0 1
device=none
T 77750 75500 5 8 0 0 90 0 1
graphical=1
]
C 72000 73400 1 90 0 EMBEDDEDgnd-1.sym
[
P 71900 73500 71700 73500 1 0 1
{
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pinnumber=1
T 71839 73558 5 4 0 0 90 0 1
pinseq=1
}
L 71900 73400 71900 73600 3 0 0 0 -1 -1
L 71950 73455 71950 73545 3 0 0 0 -1 -1
L 71990 73480 71990 73520 3 0 0 0 -1 -1
T 71950 73700 8 10 0 0 90 0 1
net=GND:1
]
N 70750 79300 71700 79300 4
N 70750 73700 71700 73700 4
N 70750 73500 71700 73500 4
N 71700 77900 70750 77900 4
N 71700 80100 70750 80100 4
N 71700 75500 70750 75500 4
N 70750 75100 71700 75100 4
N 71700 74700 70750 74700 4
N 70750 74300 71700 74300 4
N 70750 73900 71700 73900 4
N 71700 79900 70750 79900 4
N 71700 79700 70750 79700 4
N 71700 79500 70750 79500 4
N 71700 79100 70750 79100 4
N 71700 78500 70750 78500 4
N 71700 78300 70750 78300 4
N 71700 76300 70750 76300 4
N 71700 76700 70750 76700 4
N 71700 75900 70750 75900 4
N 71700 75700 70750 75700 4
N 70750 77300 71700 77300 4
N 70750 77700 71700 77700 4
T 87975 80275 9 10 1 0 0 0 3
FUSE:
  WICKMAN 3851125044
  DIGIKEY WK4564BK-ND
C 84500 68800 1 0 0 bf-gnd-1.sym
C 90700 70700 1 0 0 EMBEDDEDheader14.sym
[
P 90200 73200 89900 73200 1 0 1
{
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V 90300 73200 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 89900 73400 90300 73400 1 0 0
{
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L 90300 73400 90600 73300 3 0 0 0 -1 -1
P 90200 72800 89900 72800 1 0 1
{
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P 89900 73000 90300 73000 1 0 0
{
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L 90300 73000 90600 72900 3 0 0 0 -1 -1
P 90200 72400 89900 72400 1 0 1
{
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T 90200 72400 5 10 0 1 0 6 1
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}
P 89900 72600 90300 72600 1 0 0
{
T 90100 72625 5 10 1 1 0 6 1
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pintype=pas
T 89500 72600 5 10 0 1 0 6 1
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T 89500 72600 5 10 0 1 0 6 1
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}
P 90200 72000 89900 72000 1 0 1
{
T 90100 72025 5 10 1 1 0 6 1
pinnumber=8
T 90200 72000 5 10 0 1 0 6 1
pintype=pas
T 90200 72000 5 10 0 1 0 6 1
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T 90200 72000 5 10 0 1 0 6 1
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}
P 89900 72200 90300 72200 1 0 0
{
T 90100 72225 5 10 1 1 0 6 1
pinnumber=7
T 89500 72200 5 10 0 1 0 6 1
pintype=pas
T 89500 72200 5 10 0 1 0 6 1
pinlabel=7
T 89500 72200 5 10 0 1 0 6 1
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}
P 90200 71600 89900 71600 1 0 1
{
T 90175 71625 5 10 1 1 0 6 1
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T 90200 71600 5 10 0 1 0 6 1
pintype=pas
T 90200 71600 5 10 0 1 0 6 1
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T 90200 71600 5 10 0 1 0 6 1
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P 89900 71800 90300 71800 1 0 0
{
T 90100 71825 5 10 1 1 0 6 1
pinnumber=9
T 89500 71800 5 10 0 1 0 6 1
pintype=pas
T 89500 71800 5 10 0 1 0 6 1
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T 89500 71800 5 10 0 1 0 6 1
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}
P 90200 71200 89900 71200 1 0 1
{
T 90175 71225 5 10 1 1 0 6 1
pinnumber=12
T 90200 71200 5 10 0 1 0 6 1
pintype=pas
T 90200 71200 5 10 0 1 0 6 1
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T 90200 71200 5 10 0 1 0 6 1
pinseq=12
}
P 89900 71400 90300 71400 1 0 0
{
T 90175 71425 5 10 1 1 0 6 1
pinnumber=11
T 89500 71400 5 10 0 1 0 6 1
pintype=pas
T 89500 71400 5 10 0 1 0 6 1
pinlabel=11
T 89500 71400 5 10 0 1 0 6 1
pinseq=11
}
P 90200 70800 89900 70800 1 0 1
{
T 90150 70825 5 10 1 1 0 6 1
pinnumber=14
T 90200 70800 5 10 0 1 0 6 1
pintype=pas
T 90200 70800 5 10 0 1 0 6 1
pinlabel=14
T 90200 70800 5 10 0 1 0 6 1
pinseq=14
}
P 89900 71000 90300 71000 1 0 0
{
T 90175 71025 5 10 1 1 0 6 1
pinnumber=13
T 89500 71000 5 10 0 1 0 6 1
pintype=pas
T 89500 71000 5 10 0 1 0 6 1
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T 89500 71000 5 10 0 1 0 6 1
pinseq=13
}
V 90300 72800 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 90600 73200 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 90600 72800 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 90600 72400 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 90300 72600 90600 72500 3 0 0 0 -1 -1
V 90300 72400 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 90600 72000 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 90300 72200 90600 72100 3 0 0 0 -1 -1
V 90300 72000 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 90600 71600 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 90300 71800 90600 71700 3 0 0 0 -1 -1
V 90300 71600 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 90600 71200 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 90300 71400 90600 71300 3 0 0 0 -1 -1
V 90300 71200 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 90600 70800 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
L 90300 71000 90600 70900 3 0 0 0 -1 -1
V 90300 70800 94 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 90650 73450 8 10 0 1 0 6 1
refdes=J105
T 87800 71000 8 10 0 0 0 6 1
footprint=dheader_7x2_100_mils
T 87800 71200 8 10 0 0 0 6 1
numslots=0
T 87800 71400 8 10 0 0 0 6 1
device=header14
]
{
T 91100 73750 5 10 1 1 0 6 1
refdes=J106
T 90650 73450 5 10 1 1 0 0 1
description=JTAG
T 89800 73750 5 10 1 1 0 0 1
footprint=HD_7x2
}
N 89900 72200 89250 72200 4
N 89250 71800 89900 71800 4
N 89900 71400 89250 71400 4
N 89900 71000 89250 71000 4
N 89900 72800 89400 72800 4
N 89900 72600 89250 72600 4
C 88950 71100 1 270 0 EMBEDDEDgnd-1.sym
[
P 89050 71000 89250 71000 1 0 1
{
T 89111 70942 5 4 0 1 270 0 1
pinnumber=1
T 89111 70942 5 4 0 0 270 0 1
pinseq=1
}
L 89050 71100 89050 70900 3 0 0 0 -1 -1
L 89000 71045 89000 70955 3 0 0 0 -1 -1
L 88960 71020 88960 70980 3 0 0 0 -1 -1
T 89000 70800 8 10 0 0 270 0 1
net=GND:1
]
C 88600 73700 1 90 0 bf-resistor-1.sym
{
T 88250 74900 5 10 1 1 0 0 1
refdes=R116
T 88600 73700 5 10 0 0 90 0 1
footprint=R0603
T 88550 74450 5 10 1 1 0 0 1
value=10k
T 88600 73700 5 10 0 0 0 0 1
comment=0.125W 5%
}
C 89150 73700 1 90 0 bf-resistor-1.sym
{
T 88950 74900 5 10 1 1 0 0 1
refdes=R117
T 89150 73700 5 10 0 0 90 0 1
footprint=R0603
T 89100 74450 5 10 1 1 0 0 1
value=10k
T 89150 73700 5 10 0 0 0 0 1
comment=0.125W 5%
}
C 89700 73700 1 90 0 bf-resistor-1.sym
{
T 89800 74350 5 10 1 1 0 0 1
refdes=R118
T 89700 73700 5 10 0 0 90 0 1
footprint=R0603
T 89800 74050 5 10 1 1 0 0 1
value=10k
T 89700 73700 5 10 0 0 0 0 1
comment=0.125W 5%
}
N 83100 73500 82300 73500 4
{
T 82500 73500 5 10 1 1 0 0 1
netname=nTMS
}
N 83100 73300 82300 73300 4
{
T 82500 73300 5 10 1 1 0 0 1
netname=nTCK
}
N 83100 73700 82300 73700 4
{
T 82500 73700 5 10 1 1 0 0 1
netname=nTDI
}
N 83100 73100 82300 73100 4
{
T 82500 73100 5 10 1 1 0 0 1
netname=nTDO
}
N 82300 73900 83100 73900 4
{
T 82500 73900 5 10 1 1 0 0 1
netname=nTRS
}
N 89900 72400 88650 72400 4
{
T 89350 72400 5 10 1 1 0 0 1
netname=nTMS
}
N 89600 73400 89600 73700 4
N 77650 77800 79500 77800 4
N 75100 69100 76750 69100 4
{
T 75500 69100 5 10 1 1 0 0 1
netname=BD0
}
N 76750 68900 75100 68900 4
{
T 75500 68900 5 10 1 1 0 0 1
netname=BD1
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N 79500 69600 78050 69600 4
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N 79500 69200 78050 69200 4
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N 79500 68400 78050 68400 4
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N 79500 68000 78050 68000 4
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N 88350 72000 88350 73700 4
N 88350 72000 89900 72000 4
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N 87850 71600 89900 71600 4
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N 89100 70800 89900 70800 4
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C 78050 72300 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 72100 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 72300 77950 72200 10 30 0 0 -1 -1
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C 78050 71900 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 72100 77950 72000 10 30 0 0 -1 -1
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C 78050 71700 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 71900 77950 71800 10 30 0 0 -1 -1
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C 78050 71500 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 71300 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 71500 77950 71400 10 30 0 0 -1 -1
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C 78050 70800 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 71000 77950 70900 10 30 0 0 -1 -1
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C 78050 70600 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 70800 77950 70700 10 30 0 0 -1 -1
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C 78050 70400 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 70200 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 70000 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 70200 77950 70100 10 30 0 0 -1 -1
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C 78050 69800 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 69600 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 69400 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 69200 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 69000 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 68800 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 68600 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 68400 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 68200 1 90 0 EMBEDDEDbusripper-1.sym
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C 78050 68000 1 90 0 EMBEDDEDbusripper-1.sym
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L 77850 68200 77950 68100 10 30 0 0 -1 -1
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C 78050 67800 1 90 0 EMBEDDEDbusripper-1.sym
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C 76750 69100 1 270 0 EMBEDDEDbusripper-1.sym
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L 76950 69300 76850 69200 10 30 0 0 -1 -1
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C 76750 68900 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 68700 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 68500 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 68300 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 68100 1 270 0 EMBEDDEDbusripper-1.sym
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L 76950 68300 76850 68200 10 30 0 0 -1 -1
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C 76750 67900 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 67700 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 67500 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 67300 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 67100 1 270 0 EMBEDDEDbusripper-1.sym
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C 76750 66900 1 270 0 EMBEDDEDbusripper-1.sym
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$Revision$
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Based on the original design by David Rowe
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pr1-basic.sch
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1
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BF1 TEAM
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R115-R117 are not required for 2256 ver.2.2
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T 71800 80700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 79400 1 0 0 nc-right-1.sym
{
T 71800 79900 5 10 0 0 0 0 1
value=NoConnection
T 71800 80100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 79200 1 0 0 nc-right-1.sym
{
T 71800 79700 5 10 0 0 0 0 1
value=NoConnection
T 71800 79900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 79000 1 0 0 nc-right-1.sym
{
T 71800 79500 5 10 0 0 0 0 1
value=NoConnection
T 71800 79700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 79800 1 0 0 nc-right-1.sym
{
T 71800 80300 5 10 0 0 0 0 1
value=NoConnection
T 71800 80500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 78200 1 0 0 nc-right-1.sym
{
T 71800 78700 5 10 0 0 0 0 1
value=NoConnection
T 71800 78900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 78000 1 0 0 nc-right-1.sym
{
T 71800 78500 5 10 0 0 0 0 1
value=NoConnection
T 71800 78700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 77800 1 0 0 nc-right-1.sym
{
T 71800 78300 5 10 0 0 0 0 1
value=NoConnection
T 71800 78500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 76800 1 0 0 nc-right-1.sym
{
T 71800 77300 5 10 0 0 0 0 1
value=NoConnection
T 71800 77500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 76600 1 0 0 nc-right-1.sym
{
T 71800 77100 5 10 0 0 0 0 1
value=NoConnection
T 71800 77300 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 76400 1 0 0 nc-right-1.sym
{
T 71800 76900 5 10 0 0 0 0 1
value=NoConnection
T 71800 77100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 76200 1 0 0 nc-right-1.sym
{
T 71800 76700 5 10 0 0 0 0 1
value=NoConnection
T 71800 76900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 76000 1 0 0 nc-right-1.sym
{
T 71800 76500 5 10 0 0 0 0 1
value=NoConnection
T 71800 76700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 75800 1 0 0 nc-right-1.sym
{
T 71800 76300 5 10 0 0 0 0 1
value=NoConnection
T 71800 76500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 75600 1 0 0 nc-right-1.sym
{
T 71800 76100 5 10 0 0 0 0 1
value=NoConnection
T 71800 76300 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 75400 1 0 0 nc-right-1.sym
{
T 71800 75900 5 10 0 0 0 0 1
value=NoConnection
T 71800 76100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 75200 1 0 0 nc-right-1.sym
{
T 71800 75700 5 10 0 0 0 0 1
value=NoConnection
T 71800 75900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 75000 1 0 0 nc-right-1.sym
{
T 71800 75500 5 10 0 0 0 0 1
value=NoConnection
T 71800 75700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 74800 1 0 0 nc-right-1.sym
{
T 71800 75300 5 10 0 0 0 0 1
value=NoConnection
T 71800 75500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 74600 1 0 0 nc-right-1.sym
{
T 71800 75100 5 10 0 0 0 0 1
value=NoConnection
T 71800 75300 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 74400 1 0 0 nc-right-1.sym
{
T 71800 74900 5 10 0 0 0 0 1
value=NoConnection
T 71800 75100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 74200 1 0 0 nc-right-1.sym
{
T 71800 74700 5 10 0 0 0 0 1
value=NoConnection
T 71800 74900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 74000 1 0 0 nc-right-1.sym
{
T 71800 74500 5 10 0 0 0 0 1
value=NoConnection
T 71800 74700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71700 73800 1 0 0 nc-right-1.sym
{
T 71800 74300 5 10 0 0 0 0 1
value=NoConnection
T 71800 74500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 70800 1 0 0 nc-right-1.sym
{
T 71750 71300 5 10 0 0 0 0 1
value=NoConnection
T 71750 71500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 70600 1 0 0 nc-right-1.sym
{
T 71750 71100 5 10 0 0 0 0 1
value=NoConnection
T 71750 71300 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 70400 1 0 0 nc-right-1.sym
{
T 71750 70900 5 10 0 0 0 0 1
value=NoConnection
T 71750 71100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 70000 1 0 0 nc-right-1.sym
{
T 71750 70500 5 10 0 0 0 0 1
value=NoConnection
T 71750 70700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 69600 1 0 0 nc-right-1.sym
{
T 71750 70100 5 10 0 0 0 0 1
value=NoConnection
T 71750 70300 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 69400 1 0 0 nc-right-1.sym
{
T 71750 69900 5 10 0 0 0 0 1
value=NoConnection
T 71750 70100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 69200 1 0 0 nc-right-1.sym
{
T 71750 69700 5 10 0 0 0 0 1
value=NoConnection
T 71750 69900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 69000 1 0 0 nc-right-1.sym
{
T 71750 69500 5 10 0 0 0 0 1
value=NoConnection
T 71750 69700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 68800 1 0 0 nc-right-1.sym
{
T 71750 69300 5 10 0 0 0 0 1
value=NoConnection
T 71750 69500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 68200 1 0 0 nc-right-1.sym
{
T 71750 68700 5 10 0 0 0 0 1
value=NoConnection
T 71750 68900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 68000 1 0 0 nc-right-1.sym
{
T 71750 68500 5 10 0 0 0 0 1
value=NoConnection
T 71750 68700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 67800 1 0 0 nc-right-1.sym
{
T 71750 68300 5 10 0 0 0 0 1
value=NoConnection
T 71750 68500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 66200 1 0 0 nc-right-1.sym
{
T 71750 66700 5 10 0 0 0 0 1
value=NoConnection
T 71750 66900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 71650 66000 1 0 0 nc-right-1.sym
{
T 71750 66500 5 10 0 0 0 0 1
value=NoConnection
T 71750 66700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 71000 1 0 0 nc-right-1.sym
{
T 76100 71500 5 10 0 0 0 0 1
value=NoConnection
T 76100 71700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 70800 1 0 0 nc-right-1.sym
{
T 76100 71300 5 10 0 0 0 0 1
value=NoConnection
T 76100 71500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 70600 1 0 0 nc-right-1.sym
{
T 76100 71100 5 10 0 0 0 0 1
value=NoConnection
T 76100 71300 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 70400 1 0 0 nc-right-1.sym
{
T 76100 70900 5 10 0 0 0 0 1
value=NoConnection
T 76100 71100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 70200 1 0 0 nc-right-1.sym
{
T 76100 70700 5 10 0 0 0 0 1
value=NoConnection
T 76100 70900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 70000 1 0 0 nc-right-1.sym
{
T 76100 70500 5 10 0 0 0 0 1
value=NoConnection
T 76100 70700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 69800 1 0 0 nc-right-1.sym
{
T 76100 70300 5 10 0 0 0 0 1
value=NoConnection
T 76100 70500 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 69600 1 0 0 nc-right-1.sym
{
T 76100 70100 5 10 0 0 0 0 1
value=NoConnection
T 76100 70300 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 69400 1 0 0 nc-right-1.sym
{
T 76100 69900 5 10 0 0 0 0 1
value=NoConnection
T 76100 70100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 76000 69200 1 0 0 nc-right-1.sym
{
T 76100 69700 5 10 0 0 0 0 1
value=NoConnection
T 76100 69900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 74450 78200 1 180 0 nc-right-1.sym
{
T 74350 77700 5 10 0 0 180 0 1
value=NoConnection
T 74350 77500 5 10 0 0 180 0 1
device=DRC_Directive
}
C 79000 75100 1 0 0 nc-left-1.sym
{
T 79000 75500 5 10 0 0 0 0 1
value=NoConnection
T 79000 75900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 84900 78400 1 0 0 nc-left-1.sym
{
T 84900 78800 5 10 0 0 0 0 1
value=NoConnection
T 84900 79200 5 10 0 0 0 0 1
device=DRC_Directive
}
C 84900 76900 1 0 0 nc-left-1.sym
{
T 84900 77300 5 10 0 0 0 0 1
value=NoConnection
T 84900 77700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 86650 78400 1 0 0 nc-right-1.sym
{
T 86750 78900 5 10 0 0 0 0 1
value=NoConnection
T 86750 79100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 86650 76900 1 0 0 nc-right-1.sym
{
T 86750 77400 5 10 0 0 0 0 1
value=NoConnection
T 86750 77600 5 10 0 0 0 0 1
device=DRC_Directive
}
C 89500 77800 1 0 0 nc-left-1.sym
{
T 89500 78200 5 10 0 0 0 0 1
value=NoConnection
T 89500 78600 5 10 0 0 0 0 1
device=DRC_Directive
}
C 89500 77200 1 0 0 nc-left-1.sym
{
T 89500 77600 5 10 0 0 0 0 1
value=NoConnection
T 89500 78000 5 10 0 0 0 0 1
device=DRC_Directive
}
C 89500 77000 1 0 0 nc-left-1.sym
{
T 89500 77400 5 10 0 0 0 0 1
value=NoConnection
T 89500 77800 5 10 0 0 0 0 1
device=DRC_Directive
}
C 89500 76800 1 0 0 nc-left-1.sym
{
T 89500 77200 5 10 0 0 0 0 1
value=NoConnection
T 89500 77600 5 10 0 0 0 0 1
device=DRC_Directive
}
C 82300 74400 1 0 0 nc-right-1.sym
{
T 82400 74900 5 10 0 0 0 0 1
value=NoConnection
T 82400 75100 5 10 0 0 0 0 1
device=DRC_Directive
}
C 84400 73000 1 180 0 nc-right-1.sym
{
T 84300 72500 5 10 0 0 180 0 1
value=NoConnection
T 84300 72300 5 10 0 0 180 0 1
device=DRC_Directive
}
C 88750 73100 1 0 0 nc-left-1.sym
{
T 88750 73500 5 10 0 0 0 0 1
value=NoConnection
T 88750 73900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 88750 72900 1 0 0 nc-left-1.sym
{
T 88750 73300 5 10 0 0 0 0 1
value=NoConnection
T 88750 73700 5 10 0 0 0 0 1
device=DRC_Directive
}
C 84400 70000 1 270 0 capacitor-2.sym
{
T 85100 69800 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 84100 69700 5 10 1 1 0 0 1
refdes=CP1
T 85300 69800 5 10 0 0 270 0 1
symversion=0.1
T 84100 69200 5 10 1 1 0 0 1
value=10uF
T 84400 70000 5 10 0 0 0 0 1
footprint=CASE_A
}
C 85200 70000 1 270 0 capacitor-2.sym
{
T 85900 69800 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 84900 69700 5 10 1 1 0 0 1
refdes=CP2
T 86100 69800 5 10 0 0 270 0 1
symversion=0.1
T 84900 69200 5 10 1 1 0 0 1
value=10uF
T 85200 70000 5 10 0 0 0 0 1
footprint=CASE_A
}
C 90400 70000 1 270 0 capacitor-2.sym
{
T 91100 69800 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 90200 69700 5 10 1 1 0 0 1
refdes=CP3
T 91300 69800 5 10 0 0 270 0 1
symversion=0.1
T 90200 69300 5 10 1 1 0 0 1
value=10uF
T 90400 70000 5 10 0 0 0 0 1
footprint=CASE_A
}
C 70900 71900 1 0 0 bf-gnd-1.sym
C 71700 71900 1 0 0 bf-gnd-1.sym
N 71000 72300 71000 72200 4
N 71800 72300 71800 72200 4
C 70800 72300 1 0 0 hole.sym
{
T 70350 72300 5 10 0 1 0 0 1
device=HOLE
T 70750 72900 5 10 1 1 0 4 1
refdes=H1
T 70350 72300 5 10 0 0 0 0 1
footprint=HOLE
}
C 71600 72300 1 0 0 hole.sym
{
T 71600 72300 5 10 0 1 0 0 1
device=HOLE
T 71600 72900 5 10 1 1 0 4 1
refdes=H2
T 71600 72300 5 10 0 0 0 0 1
footprint=HOLE
}
T 84400 71898 9 10 1 0 0 0 2
2256 rev 2.1 or lower 
requires 8.192MHz
C 87000 68150 1 270 0 capacitor-2.sym
{
T 87700 67950 5 10 0 0 270 0 1
device=POLARIZED_CAPACITOR
T 86800 67850 5 10 1 1 0 0 1
refdes=CP4
T 87900 67950 5 10 0 0 270 0 1
symversion=0.1
T 87000 68150 5 10 0 0 0 0 1
description=Tantalum Cap
T 86800 67450 5 10 1 1 0 0 1
value=47uF
T 87000 68150 5 10 0 0 0 0 1
footprint=CASE_B
}
C 87100 66950 1 0 0 bf-gnd-1.sym
C 86400 69100 1 90 0 bf-capacitor-1.sym
{
T 85800 69400 5 10 0 0 90 0 1
device=CAPACITOR
T 86200 69800 5 10 1 1 180 0 1
refdes=C105
T 86400 69100 5 10 0 0 0 0 1
footprint=C0603
T 85700 69300 5 10 1 1 0 0 1
value=0.1uF
T 86100 68700 5 10 0 0 0 0 1
comment=ceramic
}
C 87000 69100 1 90 0 bf-capacitor-1.sym
{
T 86400 69400 5 10 0 0 90 0 1
device=CAPACITOR
T 86800 69800 5 10 1 1 180 0 1
refdes=C106
T 86300 69300 5 10 1 1 0 0 1
value=0.1uF
T 87000 69100 5 10 0 0 0 0 1
footprint=C0603
T 87000 69100 5 10 0 0 0 0 1
comment=ceramic
}
C 88850 67250 1 90 0 bf-capacitor-1.sym
{
T 88750 67850 5 10 1 1 0 0 1
refdes=C112
T 88750 67450 5 10 1 1 0 0 1
value=0.47uF
T 88850 67250 5 10 0 0 90 0 1
footprint=C0603
T 88850 67250 5 10 0 0 0 0 1
comment=Ceramic
}
N 88650 68150 87200 68150 4
{
T 88650 68150 5 10 0 0 0 0 1
netname=VCC
}
N 88650 67250 87200 67250 4
N 70750 78700 73300 78700 4
{
T 70975 78709 5 10 1 1 0 0 1
netname=DR0PRI
}
C 72650 81350 1 180 0 bf-gnd-1.sym
{
T 72650 81350 5 10 1 1 0 0 1
=
}
N 71650 70900 70750 70900 4
N 71650 70700 70750 70700 4
N 71650 70500 70750 70500 4
N 71650 70100 70750 70100 4
N 71650 69700 70750 69700 4
N 71650 69500 70750 69500 4
N 71650 69300 70750 69300 4
N 71650 69100 70750 69100 4
N 71650 68900 70750 68900 4
N 71650 68300 70750 68300 4
N 71650 68100 70750 68100 4
N 71650 67900 70750 67900 4
N 71650 66300 70750 66300 4
N 71650 66100 70750 66100 4
N 82300 75100 83250 75100 4
N 83250 75100 83250 74900 4
N 82300 75500 83250 75500 4
N 83250 75500 83250 75600 4
N 88500 74600 88500 74800 4
N 87950 71200 87950 73700 4
N 84600 70000 90600 70000 4
{
T 86200 70000 5 10 0 0 0 0 1
netname=VCC
}
N 84600 69100 90600 69100 4
C 88950 71500 1 270 0 EMBEDDEDgnd-1.sym
[
P 89050 71400 89250 71400 1 0 1
{
T 89111 71342 5 4 0 1 270 0 1
pinnumber=1
T 89111 71342 5 4 0 0 270 0 1
pinseq=1
}
L 89050 71500 89050 71300 3 0 0 0 -1 -1
L 89000 71445 89000 71355 3 0 0 0 -1 -1
L 88960 71420 88960 71380 3 0 0 0 -1 -1
T 89000 71200 8 10 0 0 270 0 1
net=GND:1
]
C 88950 71900 1 270 0 EMBEDDEDgnd-1.sym
[
P 89050 71800 89250 71800 1 0 1
{
T 89111 71742 5 4 0 1 270 0 1
pinnumber=1
T 89111 71742 5 4 0 0 270 0 1
pinseq=1
}
L 89050 71900 89050 71700 3 0 0 0 -1 -1
L 89000 71845 89000 71755 3 0 0 0 -1 -1
L 88960 71820 88960 71780 3 0 0 0 -1 -1
T 89000 71600 8 10 0 0 270 0 1
net=GND:1
]
C 88950 72300 1 270 0 EMBEDDEDgnd-1.sym
[
P 89050 72200 89250 72200 1 0 1
{
T 89111 72142 5 4 0 1 270 0 1
pinnumber=1
T 89111 72142 5 4 0 0 270 0 1
pinseq=1
}
L 89050 72300 89050 72100 3 0 0 0 -1 -1
L 89000 72245 89000 72155 3 0 0 0 -1 -1
L 88960 72220 88960 72180 3 0 0 0 -1 -1
T 89000 72000 8 10 0 0 270 0 1
net=GND:1
]
C 89100 72900 1 270 0 EMBEDDEDgnd-1.sym
[
P 89200 72800 89400 72800 1 0 1
{
T 89261 72742 5 4 0 1 270 0 1
pinnumber=1
T 89261 72742 5 4 0 0 270 0 1
pinseq=1
}
L 89200 72900 89200 72700 3 0 0 0 -1 -1
L 89150 72845 89150 72755 3 0 0 0 -1 -1
L 89110 72820 89110 72780 3 0 0 0 -1 -1
T 89150 72600 8 10 0 0 270 0 1
net=GND:1
]
C 86850 71300 1 0 0 EMBEDDEDgnd-1.sym
[
P 86950 71400 86950 71600 1 0 1
{
T 87008 71461 5 4 0 1 0 0 1
pinnumber=1
T 87008 71461 5 4 0 0 0 0 1
pinseq=1
}
L 86850 71400 87050 71400 3 0 0 0 -1 -1
L 86905 71350 86995 71350 3 0 0 0 -1 -1
L 86930 71310 86970 71310 3 0 0 0 -1 -1
T 87150 71350 8 10 0 0 0 0 1
net=GND:1
]
N 87950 71200 89900 71200 4
{
T 89350 71200 5 10 1 1 0 0 1
netname=nTDI
}
N 89900 73000 89250 73000 4
N 89900 73200 89250 73200 4
N 87950 74600 87950 74800 4
N 88650 72400 88650 73550 4
N 88650 73550 89050 73550 4
N 89050 74600 89050 74800 4
N 89050 73550 89050 73700 4
N 88500 73700 88350 73700 4
N 82300 75300 84350 75300 4
N 79325 72500 79500 72500 4
N 84350 74100 84350 73700 4
N 84350 73700 84550 73700 4
N 84350 75300 84350 75000 4
N 79500 76100 79300 76100 4
C 78800 76000 1 0 0 nc-left-1.sym
{
T 78800 76400 5 10 0 0 0 0 1
value=NoConnection
T 78800 76800 5 10 0 0 0 0 1
device=DRC_Directive
}
C 84450 74100 1 90 0 bf-resistor-1.sym
{
T 84950 74850 5 10 1 1 180 0 1
refdes=R125
T 84750 74450 5 10 1 1 180 0 1
value=47
T 84450 74100 5 10 0 0 180 0 1
footprint=R0603
}
C 86350 72500 1 0 1 pr1_osc-2.sym
{
T 84450 73300 5 10 0 0 0 6 1
device=CLOCK OSC
T 84450 73000 5 10 0 0 0 6 1
footprint=CLOCK
T 86000 74050 5 10 1 1 0 6 1
refdes=X101
T 84950 73200 5 10 1 1 0 0 1
description=10.000MHz
}
C 86900 72900 1 90 0 bf-capacitor-1.sym
{
T 86800 73500 5 10 1 1 0 0 1
refdes=C102
T 86800 73100 5 10 1 1 0 0 1
value=0.1uF
T 86900 72900 5 10 0 0 90 0 1
footprint=C0603
T 86900 72900 5 10 0 0 0 0 1
comment=Ceramic
}
C 86600 72450 1 0 0 bf-gnd-1.sym
N 86350 72900 86700 72900 4
N 86350 73700 86700 73700 4
{
T 86350 73700 5 10 0 0 0 0 1
netname=VCC
}
N 86700 73700 86700 73900 4
N 86700 72750 86700 72900 4
N 84550 72900 84400 72900 4
C 82300 74200 1 0 0 nc-right-1.sym
{
T 82400 74700 5 10 0 0 0 0 1
value=NoConnection
T 82400 74900 5 10 0 0 0 0 1
device=DRC_Directive
}
N 73000 79300 73000 80550 4
N 73300 79000 72550 79000 4
N 72550 79000 72550 80550 4
N 79200 77600 79500 77600 4
N 70750 77500 72250 77500 4
{
T 70967 77500 5 10 1 1 0 0 1
netname=DT0PRI
}
N 70750 77100 72800 77100 4
{
T 70967 77117 5 10 1 1 0 0 1
netname=RSCLK0
}
N 72800 77100 72800 78400 4
N 70750 78900 72550 78900 4
{
T 70975 78900 5 10 1 1 0 0 1
netname=RFS0
}
C 76750 78300 1 0 0 resistor-1.sym
{
T 77050 78700 5 10 0 0 0 0 1
device=RESISTOR
T 76500 78450 5 10 1 1 0 0 1
refdes=R102
T 77450 78450 5 10 1 1 0 0 1
value=0
T 76750 78300 5 10 0 0 0 0 1
footprint=R0603
}
C 77650 77300 1 180 0 resistor-1.sym
{
T 77350 76900 5 10 0 0 180 0 1
device=RESISTOR
T 76950 77350 5 10 1 1 180 0 1
refdes=R121
T 77800 77350 5 10 1 1 180 0 1
value=4.7k
T 77650 77300 5 10 0 0 180 0 1
footprint=R0603
T 77650 77300 5 10 0 0 180 0 1
comment=0.125W 5%
}
C 77650 78200 1 180 0 resistor-1.sym
{
T 77350 77800 5 10 0 0 180 0 1
device=RESISTOR
T 76950 78250 5 10 1 1 180 0 1
refdes=R122
T 77800 78250 5 10 1 1 180 0 1
value=4.7k
T 77650 78200 5 10 0 0 180 0 1
footprint=R0603
T 77650 78200 5 10 0 0 180 0 1
comment=0.125W 5%
}
N 78900 79000 76450 79000 4
N 79200 79300 76450 79300 4
N 79200 79300 79200 77600 4
C 73950 77100 1 0 0 nc-left-1.sym
{
T 73950 77500 5 10 0 0 0 0 1
value=NoConnection
T 73950 77900 5 10 0 0 0 0 1
device=DRC_Directive
}
C 74200 77600 1 180 0 resistor-1.sym
{
T 73900 77200 5 10 0 0 180 0 1
device=RESISTOR
T 73450 77650 5 10 1 1 180 0 1
refdes=R105
T 74150 77650 5 10 1 1 180 0 1
value=0
T 74200 77600 5 10 0 0 180 0 1
footprint=R0603
T 74200 77600 5 10 0 0 180 0 1
comment=0.125W 5%
}
C 73300 77700 1 0 0 resistor-1.sym
{
T 73600 78100 5 10 0 0 0 0 1
device=RESISTOR
T 73000 77850 5 10 1 1 0 0 1
refdes=R108
T 74000 77850 5 10 1 1 0 0 1
value=0
T 73300 77700 5 10 0 0 0 0 1
footprint=R0603
T 73300 77700 5 10 0 0 0 0 1
comment=0.125W 5%
}
C 74200 78500 1 180 0 resistor-1.sym
{
T 73900 78100 5 10 0 0 180 0 1
device=RESISTOR
T 73450 78550 5 10 1 1 180 0 1
refdes=R107
T 74150 78550 5 10 1 1 180 0 1
value=0
T 74200 78500 5 10 0 0 180 0 1
footprint=R0603
T 74200 78500 5 10 0 0 180 0 1
comment=0.125W 5%
}
C 74200 78800 1 180 0 resistor-1.sym
{
T 73900 78400 5 10 0 0 180 0 1
device=RESISTOR
T 73450 78850 5 10 1 1 180 0 1
refdes=R106
T 74150 78850 5 10 1 1 180 0 1
value=0
T 74200 78800 5 10 0 0 180 0 1
footprint=R0603
T 74200 78800 5 10 0 0 180 0 1
comment=0.125W 5%
}
C 73300 78900 1 0 0 resistor-1.sym
{
T 73600 79300 5 10 0 0 0 0 1
device=RESISTOR
T 73000 79050 5 10 1 1 0 0 1
refdes=R124
T 74050 79050 5 10 1 1 0 0 1
value=330
T 73300 78900 5 10 0 0 0 0 1
footprint=R0603
T 73300 78900 5 10 0 0 0 0 1
comment=0.125W 5%
}
N 72800 78400 73300 78400 4
C 73300 79200 1 0 0 resistor-1.sym
{
T 73600 79600 5 10 0 0 0 0 1
device=RESISTOR
T 73100 79500 5 10 1 1 0 0 1
refdes=R123
T 73800 79500 5 10 1 1 0 0 1
value=330
T 73300 79200 5 10 0 0 0 0 1
footprint=R0603
T 73300 79200 5 10 0 0 0 0 1
comment=0.125W 5%
}
N 79500 78700 78900 78700 4
N 78900 78700 78900 77500 4
N 79500 78900 79400 78900 4
N 79400 78900 79400 78700 4
T 76900 78650 8 10 0 0 0 0 1
device=74LV244D
T 76900 78850 8 10 0 0 0 0 1
footprint=bf_SOT163_1
C 87600 68150 1 270 0 bf-capacitor-1.sym
{
T 88350 67950 5 10 1 1 180 0 1
refdes=C101
T 88400 67500 5 10 1 1 180 0 1
value=0.1uF
T 87600 68150 5 10 0 0 270 0 1
footprint=C0603
T 87600 68150 5 10 0 0 180 0 1
comment=16V X7R 20%
}
C 76750 78600 1 0 0 resistor-1.sym
{
T 77050 79000 5 10 0 0 0 0 1
device=RESISTOR
T 76500 78750 5 10 1 1 0 0 1
refdes=R103
T 77450 78750 5 10 1 1 0 0 1
value=0
T 76750 78600 5 10 0 0 0 0 1
footprint=R0603
}
N 79500 78100 78500 78100 4
N 78500 78100 78500 78700 4
C 76750 77400 1 0 0 resistor-1.sym
{
T 76500 77550 5 10 1 1 0 0 1
refdes=R101
T 77450 77550 5 10 1 1 0 0 1
value=0
T 76750 77400 5 10 0 0 0 0 1
footprint=R0603
T 76750 77400 5 10 0 0 0 0 1
comment=0.125W 5%
}
N 77650 77500 78900 77500 4
N 77650 78700 78500 78700 4
C 76750 77700 1 0 0 resistor-1.sym
{
T 77050 78100 5 10 0 0 0 0 1
device=RESISTOR
T 76500 77850 5 10 1 1 0 0 1
refdes=R104
T 77450 77850 5 10 1 1 0 0 1
value=0
T 76750 77700 5 10 0 0 0 0 1
footprint=R0603
}
N 76750 78700 76450 78700 4
N 76750 78400 76450 78400 4
N 76750 78100 76450 78100 4
N 76750 77800 76450 77800 4
N 76750 77500 76450 77500 4
N 76750 77200 76450 77200 4
N 74200 78700 74450 78700 4
N 74200 79000 74450 79000 4
N 74200 78400 74450 78400 4
N 74450 77800 74200 77800 4
N 74450 77500 74200 77500 4
N 73300 77500 72550 77500 4
N 72550 77500 72550 78900 4
N 73300 77800 72250 77800 4
N 72250 77800 72250 77500 4
C 74450 76600 1 0 0 PR1-74LV244D.sym
{
T 74750 79750 5 10 0 0 0 0 1
device=74HC244
T 76150 79600 5 10 1 1 0 6 1
refdes=U101
T 74750 79950 5 10 0 0 0 0 1
footprint=SOT163-1
}
N 73300 79300 73000 79300 4
N 74200 79300 74450 79300 4
N 79500 76700 79500 77000 4
N 75850 76600 75050 76600 4
N 79500 79100 78900 79100 4
N 78900 79100 78900 79000 4
N 72550 81050 73000 81050 4
C 89800 68150 1 0 0 generic-power.sym
{
T 89800 68450 5 10 1 1 0 0 1
netname=Vcc
}
C 87000 68150 1 0 0 generic-power.sym
{
T 87000 68450 5 10 1 1 0 0 1
netname=Vcc
}
C 78150 76850 1 0 0 generic-power.sym
{
T 78150 77150 5 10 1 1 0 0 1
netname=Vcc
}
C 77650 77400 1 270 0 generic-power.sym
{
T 77950 77400 5 10 1 1 270 0 1
netname=Vcc
}
C 77650 78300 1 270 0 generic-power.sym
{
T 77950 78300 5 10 1 1 270 0 1
netname=Vcc
}
C 79500 77100 1 90 0 generic-power.sym
{
T 79200 77100 5 10 1 1 90 0 1
netname=Vcc
}
C 71700 77500 1 270 0 generic-power.sym
{
T 72000 77500 5 10 1 1 270 0 1
netname=Vcc
}
C 71700 77900 1 270 0 generic-power.sym
{
T 72000 77900 5 10 1 1 270 0 1
netname=Vcc
}
C 89400 74800 1 0 0 generic-power.sym
{
T 89400 75100 5 10 1 1 0 0 1
netname=Vcc
}
C 86500 73900 1 0 0 generic-power.sym
{
T 86500 74200 5 10 1 1 0 0 1
netname=Vcc
}
C 89250 72400 1 90 0 generic-power.sym
{
T 88950 72400 5 10 1 1 90 0 1
netname=Vcc
}
C 84100 78300 1 0 0 generic-power.sym
{
T 84100 78600 5 10 1 1 0 0 1
netname=Vcc
}
N 85800 68100 85800 68200 4
N 85800 68200 86300 68200 4
{
T 85800 68200 5 10 1 1 0 0 1
netname=VDDC
}