v 20060123 1
L 300 100 300 700 3 0 0 0 -1 -1
L 300 700 700 700 3 0 0 0 -1 -1
T 500 800 5 10 0 0 0 0 1
device=7400
T 500 1000 5 10 0 0 0 0 1
slot=1
T 500 1200 5 10 0 0 0 0 1
numslots=4
T 500 1400 5 10 0 0 0 0 1
slotdef=1:1,2,3
T 500 1600 5 10 0 0 0 0 1
slotdef=2:4,5,6
T 500 1800 5 10 0 0 0 0 1
slotdef=3:9,10,8
T 500 2000 5 10 0 0 0 0 1
slotdef=4:12,13,11
L 300 100 700 100 3 0 0 0 -1 -1
A 700 400 300 270 180 3 0 0 0 -1 -1
V 1050 400 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1100 400 1300 400 1 0 1
{
T 1100 450 5 8 1 1 0 0 1
pinnumber=3
T 1100 350 5 8 0 1 0 2 1
pinseq=3
T 950 400 9 8 0 1 0 6 1
pinlabel=Y
T 950 400 5 8 0 1 0 8 1
pintype=out
}
P 300 200 0 200 1 0 1
{
T 200 250 5 8 1 1 0 6 1
pinnumber=2
T 200 150 5 8 0 1 0 8 1
pinseq=2
T 350 200 9 8 0 1 0 0 1
pinlabel=B
T 350 200 5 8 0 1 0 2 1
pintype=in
}
P 300 600 0 600 1 0 1
{
T 200 650 5 8 1 1 0 6 1
pinnumber=1
T 200 550 5 8 0 1 0 8 1
pinseq=1
T 350 600 9 8 0 1 0 0 1
pinlabel=A
T 350 600 5 8 0 1 0 2 1
pintype=in
}
T 300 800 8 10 1 1 0 0 1
refdes=U?
T 500 2150 5 10 0 0 0 0 1
footprint=DTSSOP-14
T 500 2350 5 10 0 0 0 0 1
description=4 NAND gates with 2 inputs
T 500 2550 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
T 0 0 8 8 0 0 0 0 1
author=Ivan Danov
T 0 0 8 8 0 0 0 0 1
email=idanov@gmail.com
T 0 0 8 8 0 0 0 0 1
dist-license=GPL
T 0 0 8 8 0 0 0 0 1
use-license=unlimited