module shift8 (clk, serial_in, parallel_out);
input        clk, serial_in;
output [7:0] parallel_out;
reg    [7:0] tmp;

  initial begin
    tmp = 0;
  end

  always @(posedge clk)
  begin
    tmp = {tmp[6:0], serial_in};
  end
  assign parallel_out = tmp;
endmodule