/*
   ip08_cpld.c
   Created 11 Nov 2007 by David Rowe

   XC9572 CPLD logic for IP08 IP-PBX.  

   Functions:
     + decodes NAND Flash/Eth0/Eth1/USB
     + decodes SPI chip selects for 8 modules
     + routes SPORT1 to module SPI
     + decodes bi-color LED signals for 8 LEDs
*/

/*
*
* This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 
 *
 */

/*
  Revision history:
	when	        who	        what's changed/fixed
	------- 	-------	        ---------------------------------
        2007.11.15	David Rowe 	IP04->IP08 port
*/

/*
    For more information on the 4fx logic, see the cpld directory of 
    hardware-x.y.tar.gz from http://www.rowetel.com/ucasterisk/downloads.
*/

module ip08_cpld(
	// address decoding inputs

       	AMS0   ,
       	AMS1   ,
       	AMS2   ,
	AMS3   ,
        ARE    ,
        AOE    ,
       	AWE    ,

	// address decoding outputs

	NANDCE ,
       	CSETH0 ,
       	CSETH1 ,
       	CSUSB  ,
	RDUSB  ,
       	WRUSB  ,

	// module decoding

        PF8    ,            // nCSA for SPORT-over-SPI
        PF9    ,            // nCSB for SPORT-over-SPI

  	DT1    ,            
 	DR1    ,
	FS1    ,
  	CLK1   ,
  	nCS8_1 ,            // 8 external chip selects for modules
  	LED_out,            // two bits to each LED, allows bicolor operation
       
  	//BBSCLK ,            // SPI clock to modules
	BBSCLK1, BBSCLK2, BBSCLK3, BBSCLK4,
  	BBSDO  ,            // SPI SDO to modules
  	BBSDI  ,            // SPI SDI to modules

	// presently unused

	SCLK   ,
	SDO    ,
	SDO_A  ,
	SDI    ,
        SPIFLASH,
	_nCSA  ,            // nCSA for earlier SPI hardware            
  	_nCSB  ,            // NCSB for earlier SPI hardware
        PF11   ,          
        A17    ,
        A18    ,
        A19    ,
        SDRAM_CLK,
        ARDY   
);

// Port directions begin here
input AMS0 ;
input AMS1 ;
input AMS2 ;
input AMS3 ;
input ARE ;
input AOE ;
input AWE ;

output NANDCE ;
output CSETH0 ;
output CSETH1 ;
output CSUSB ;
output RDUSB ;
output WRUSB ;

input  PF8  ;
input  PF9  ;
input  FS1  ;
input  DT1  ;
input  CLK1 ;

output  DR1;
output [7:0] nCS8_1;
output [15:0] LED_out;

//output BBSCLK;
output BBSCLK1, BBSCLK2, BBSCLK3, BBSCLK4;
input  BBSDO;
output BBSDI;

// presently unused, assign as input

input	SCLK;
input	SDO;
input	SDO_A;
input	SDI;
input   SPIFLASH;
input  _nCSA ;
input  _nCSB ;
input   PF11;
input   A17;
input   A18;
input   A19;
input   SDRAM_CLK;
input   ARDY;

// internal signals

wire         nCSA, nCSB;
wire   [7:0] sr1_out;  
wire   [7:0] sr2_out;  
wire         nCS5_1, nCS5_2;  // chip selects for internal LED registers
wire         nCS0_1, nCS0_2;  // unsused chip selects (formerly for MMC)

wire   [7:0] nCS8_1;
wire  [15:0] LED_out;
wire         nCS_1, nCS_2;
wire         sclk, nSYS, nPWR;

// NAND Flash

assign NANDCE = AMS0; // 0x2000 0000

// Ethernet

assign CSETH0 = AMS1; // 0x2010 0000
assign CSETH1 = AMS2; // 0x2020 0000

// USB

assign CSUSB = AMS3;  // 0x2030 0000
assign RDUSB = ARE;
assign WRUSB = CSUSB || AWE;

// The logic below is derived from the 4fx card design.  Keeping
// consistent with the design means the current drivers (wcfxs.c
// etc) will work unmodified and be backwards compatable.  We
// use Alex Tao's SPI-over-SPORT1 design for module SPI comms to
// free the SPI bus for the MMC card.

assign nCSA = PF8;
assign nCSB = PF9;
assign nPWR = _nCSB; 
assign nSYS = (!nPWR) | FS1;
assign sclk = nSYS | CLK1;

// 4fx logic - ports 1:4 --------------------------------------

assign nCS_1 = (!(sr1_out[7:6] == 2'b00))|(!nPWR) | nCSA;

// register for nCSx selection
// format is D7 D6 D5 D4 D3 D2 D1 D0
//           A7 A6  X  X  X A2 A1 A0
// A[7:6] select this card from other cards on SPI bus, we hard code 
//        to 00 as this is the base card in the stack
// A[2:0] select the SPI device on this card (only 5 devices decoded)
 
shift8 sr_1(
.cs           (nCSB),
.clk          (sclk),
.serial_in    (DT1),
.parallel_out (sr1_out)
);

// decodes sr1 output to choose nCSx
// only valid if address bits A match

demux3x5 my_demux3x5_1(
.din    (nCS_1),
.select (sr1_out[2:0]),
.dout   ({nCS5_1,nCS8_1[3:0],nCS0_1})
);

// register for LED control

shift8 ledreg_1(
.cs           (nCS5_1),
.clk          (sclk),
.serial_in    (DT1),
.parallel_out (LED_out[7:0])
);

// 4fx logic - ports 5:8 --------------------------------------

assign nCS_2 = (!(sr2_out[7:6] == 2'b01))|(!nPWR) | nCSA;

// register for nCSx selection
// format is D7 D6 D5 D4 D3 D2 D1 D0
//           A7 A6  X  X  X A2 A1 A0
// A[7:6] select this card from other cards on SPI bus, we hard code 
//        to 00 as this is the base card in the stack
// A[2:0] select the SPI device on this card (only 5 devices decoded)
 
shift8 sr_2(
.cs           (nCSB),
.clk          (sclk),
.serial_in    (DT1),
.parallel_out (sr2_out)
);

// decodes sr1 output to choose nCSx
// only valid if address bits A match

demux3x5 my_demux3x5_2(
.din    (nCS_2),
.select (sr2_out[2:0]),
.dout   ({nCS5_2,nCS8_1[7:4],nCS0_2})
);

// register for LED control

shift8 ledreg_2(
.cs           (nCS5_2),
.clk          (sclk),
.serial_in    (DT1),
.parallel_out (LED_out[15:8])
);

// SPORT1 is used for SPI communications to the modules,
// this logic routes the SPORT signals to the module SPI
// bus

//assign BBSCLK = sclk;
assign BBSCLK1 = sclk;
assign BBSCLK2 = sclk;
assign BBSCLK3 = sclk;
assign BBSCLK4 = sclk;
assign BBSDI = DT1;
assign DR1 = BBSDO;

endmodule