// IP04 v0.0.1 CPLD verilog code
// started: March 31 2007
// written by David Rowe
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
//
// Revision history:
//	when	who	what's changed/fixed
//	-------	-------	---------------------------------------------------
//	073108	DR	first release


/*
    This module combines the logic from the 4fx CPLD and a much reduced
    version of the BlackfinOne v2 address decoding logic.  For more
    information on the 4fx logic, see the cpld directory of 
    hardware-x.y.tar.gz from http://www.rowetel.com/ucasterisk/downloads.
*/

module ip04_cpld(
  nCSA,               // assert this to talk to SPI devices
  nCSB,               // assert this to select SPI device
  SDI, 
  SDO,
  SCLK,
  nCS4_0,             // 4 external chip selects
  LED_out,            // two bits to each LED, allows bicolor operation
       
  BBSCLK,             // Bit bashed SPI clock
  BBSDO,              // Bit bashed SPI SDO
  BBSDI,              // Bit bashed SPI SDI
  SPIFLASH            // assrted low when SPI flash enabled
);

input  nCSA, nCSB, SDI, SCLK;
inout  SDO;
output [4:0] nCS4_0;
wire   [4:0] nCS4_0;
output [7:0] LED_out;
wire   [7:0] LED_out;
wire         nCS;

output BBSCLK;
input BBSDO;
output BBSDI;
input SPIFLASH;

// internal signals

wire   [7:0] sr1_out;  
wire         nCS5;     // chip select for internal LED register
wire         sr1_clk;
wire         sr2_clk;

// Logic from the 4fx CPLD -----------------------------------------

assign sr1_clk = nCSB | SCLK;
assign nCS     = !(!nCSA & (sr1_out[7:6] == 2'b00));
assign sr2_clk = nCS5 | SCLK;

// register for nCSx selection
// format is D7 D6 D5 D4 D3 D2 D1 D0
//           A7 A6  X  X  X A2 A1 A0
// A[7:6] select this card from other cards on SPI bus, we hard code 
//        to 00 as this is the base card in the stack
// A[2:0] select the SPI device on this card (only 5 devices decoded)
 
shift8 sr1(
.clk          (sr1_clk),
.serial_in    (SDI),
.parallel_out (sr1_out)
);

// decodes sr1 output to choose nCSx
// only valid if address bits A match

demux3x5 my_demux3x5(
.din    (nCS),
.select (sr1_out[2:0]),
.dout   ({nCS5,nCS4_0})
);

// register for LED control

shift8 sr2(
.clk          (sr2_clk),
.serial_in    (SDI),
.parallel_out (LED_out)
);

// SPI routing logic -------------------------------------------

// default to HW SPI as we will not be using MMC for a while
// when SPIFLASH asserted (L) disable SDO, this prevents
// contention at boot time

bufif1 ob1(SDO, BBSDO, SPIFLASH);
assign BBSCLK = SCLK;
assign BBSDI = SDI;

endmodule