[X] Consider replacing thru holes with SM + to lower assembly costs as SM much cheaper to solder [X] Xtals + might leav these as thru hole as cheap + only 4 more wires [X] PS caps + in this size/voltage think we stick with thru hole [X] LEDs + consider changing these later, for example different form factor LED to match box [X] Consider recrystal BF1 to derive serial clocks + save cost be reducing number of xtal osc [-] test on BF1 + e.g. generate serial clock as divisor + doesnt have to be the exact frequency + just prove it can be don eif we have the right xtal + as an alternative use CPLD to divide down [X] For now I will add the regular osc they are only $1.50 + we can try removing this part later (include a series terminator) and doing the above tests [ ] Pullups consistent values + less reels to load + check changes OK with bfin forum, some changes might be sensitive [ ] Schematic [X] Strip down bf1 [X] set boot mode by 0603s or header + reduce thru hole soldering in production + actually default (no links) is boot from SPI eeprom/flash + so we can just leave J1-J2 DNL [X] Mark DNLs + mark on schematic so we can extract automatically + comment = DNL [X] D12 LED [X] J5 (34 way serial/SPI) J6 (SD card) GPIO [X] BFJTAG1 & BFJTAG2 + we will use a special jack to program that fits in holes, save soldering [X] Project name and author on each sheet [X] eth and NAND flash connected to unbuffered bus [X] find for cheaper MAX232 equiv + US$1.50 from Digikey in Qty100, actually not too bad + only need two pins [X] Check if OK to leave RTS/CTS pins floating. + data sheet says RS232 inputs have pull ups, but logic side need to be tied. I will tie the two inputs together. [X] simplified RS232 wiring to basic 3 wire circuit. + hope this didn't kill anything! + control signals werent being used anyway. [X] break out GPIOs like spare on ethernet and bf to DNL header [X] route all SPI signals thru CPLD [X] Renumber chips sensibly [X] Check NAND flash connections against AD ref design + found A1-A2 swapped, corrected [-] Check if U1 VDDRTC can be left o/c + left open on bf1 [-] small JTAG connectors, like 4-6 pins + decided to stick with teh full size ones as they fit OK [X] Resolve refdes clashes between bf1 and 4fx [-] Remove myriad of jumpers on 4fx [-] Document minimum fixed PFs we need [X] Provision for interrupt from modules + Yep, PF1 connected to J5 (34 way) and all modules via series term + really would be nice to test this some time, get driver modified [X] Look at CPLD logic + key thing is make sure we are compatable with bf1 drivers + dont want to have to modify them + not a problem to keep extra CPLD for 4fx if reqd + unfortunately ended up using different scheme to bf1 to make routing easier and use smaller CPLD. So we will need to modify a lot of code - added to software task list below [ ] Talk to Tom about likely SW1 part [X] get part number + ELECTUS part SP0604 [ ] get footprint + have asked Electus, but no reply so far + looks v close to that on PCB [X] Maybe use smaller PS caps, we dont need full capability of 3A I think + perhaps keep big footprint + OK I reduced them to those used on the bf1 + however height is an issue here, limit to 8mm to stop fouling with stacked 4fx + modified schem for smaller caps as per my bf1 prototype [X] Determine how big serial flash we need? + u-boot binary is only 100k [X] make sure serial flash pin out is OK - some are 8 SOIC + added SOIC U3A [X] Consider keeping xtal osc + only $1.50, saves some development + yes, will keep it as discussed above [X] some bulk C for MMC card? [-] check if R57 & ARDY still reqd + no harm leaving it there I guess + could check data sheet to see if it has a pull up + well its there, we dont have to load it [X] encode SVN release tag into sch files [X] make file to generate PDFs of schem + drive gschem from cmd line to generate PS files + run ps-pdf converter [X] CLKOUT and RTC batt test-point/vias [X] Synthesise CPLD logic + make sure it synthesises before committing to copper + just in case we sont have enough logic, or have a dud pin [X] baseline logic synthesises OK + not using PF or 2nd serial port pins, so there is a danger these might be wired to the wrong pins or something + BB SPI connected to HW SPI + using correct pinout in UCF file [X] do we need a weak pull up on MMSDO, BBSDO inputs of CPLD + will be floating otherwise when SPI devices aren't driving + does the CPLD have weak pullups? + yes, according to the XC9536 data sheet, there is a pull up on each pin but it is disabled during normal operation + added pull ups [X] Consider removing (or bypassing in production) + add up BOM cost + do EMI test without these parts [X] T4 ferrite + Talk to Tom, is it possible to load 0603s on top of parts automatically? + I think that would require either manual load or a new solder mask [X] consider using 2nd serial port as SPI port + hooked it up to the CPLD + big job on PCB! [ ] PCB [X] Strip down bf1 [X] Make sure no solder allowed in SD card lug holes + these were being filled by solder on 4fx causing load probs + manually edited PCB and footprint files with text editor [X] Make all mounting holes the same size + close enough, within 0.05mm [X] line up all mounting holes, sensible number of mm apart [X] Need a design decision on SPI for flash/zaptel + nice to route thru CPLD if possible + by routing SPI lines thru zaptel both options are open [X] BOM spreadsheet to estimate cost [X] Consider simpler reset circuit based on RC/CPLD + ask about this on the bf1 mailing list + prototype + Dimitar convinced me best to stick with supervisiors + this device is likely to go in remote, poor power areas + A watchdog can't catch all events, e.g. its clock may be stopped by a brown out [X] reconsider reset button + no harm in having footprint + have it as DNL [X] Change Layout name [X] All designators facing the same way [X] C97 220uF 6V Ethernet cap package + check with Tom see if there is a mreo sensible package + yes a D case package, need to find one + OK found one dimensions are 7.3 x 2.2mm, which fits OK on our C48 C50 C97 (1.2V switcher) footprints [-] Penguin logo [X] collate bf1 assembly notes into this task list + covered most already + one interesting idea was to use spare pair of Ethernet to carry RS232, useful if box is remote (e.g. up a tower) [-] Legend for bootmode J1-J2 on silkscreen + not reqd as teh default (no jumpers is fine) [X] estimate height of components, check for fouling with 4fx stacked on top + guess it depends on the hegiht of the 34 way header. Might be OK actually + OK with a stack we actually have 15mm (allow 1-2mm space to not touch bottom of stacked 4fx). More if we simply use taller headers. [X] L1 - in bfin area so OK [X] L4 (PSU inductor) - needs 10mm, so OK [X] C166, C164 + about 15mm + current values OK if loaded close to board + consider insulator (like tape) on top + consider change foot print [X] work out a way to check if therms are shorting anything + replaced them all with tracks [X] Use top layer GND plane the stitch planes together, e.g. all over 4fx [X] Check that SPI/TDM nets have option for series term Rs [X] series terms for SPI signals out of CPLD + added to outputs + not worrying about SPI connections to bfin, nets are short to CPLD and MMC/SO-8 SPI flash will be rarely used, unlikely to affect EMI [X] encode SVN release tag into PCB file [X] remove thermals and replace with short track segments + thermal caused shorts on bf1 v2, DRC checker bug + not sure if this PCB bug has been fixed [-] consider top layer GND plane near bfin as per bf1 + tried laying ot over bfin, but wasnt filling much + don't think it will be very usefulso leave out [X] Extract gerbers [X] Makefile option to generate a gerber zip file with rev number [X] identify and extract that drill file I forgot last time + .cnc I think [X] Consider piggy-backing a SO-8 SPI flash package [X] determine which serial flash chips we can use + The MP26Pxx series are recc by AD on the Blackfin site [X] so I added a SO-8 foot print MP25P20 device to schem and PCB [X] Connect 2nd serial port to CPLD to allow possibility of using serial port as second SPI port. [ ] Checks [ ] NAND Flash [ ] select part [X] check pinout + yep, seem standard across many NAND flash parts [X] footprint + yes, TSOP48 on PCB checks out against data sheet [ ] check supported by linux [X] Consistent cap footprints + e.g. for 100uF, use same parts across bf1 and 4fx + might not matter too much as board stuffer will find common subsitutes that fit + done [X] SPI signal directions correct to modules [X] Check SPI signals are flowing the right way - 4fx labels are a bit confusing + they are labeled WRT to the SPI peripheral devices. This is kinda useful, as there are several SPI devices and just one master. [X] Examine CPLD combining of SPI signals, make sure no arbitration issues. + well we just combine inputs, signals flowing to the bfin (SDO). + MMCSDO & BBSDO are OR-ed together, is this OK? Mmmm, this could mean they are stuck H or L. Perhaps we need a tri-state arangement. [X] Need SDO tri-stated by CPLD to allow serial flash to drive it, say at boot time. Then default is BBSDO feed straight thru, as this will be only device on bus for first rev. OK fixed this in CPLD verilog. Was tricky - needed to work out how to define an output with OE. But have synthesised OK. Now anytime SPIENABLE is asserted (L), the SDO output of the CPLD goe HiZ. As we have a pull up on the MMC CS line, this shoudl mean the SPI flash is the only device driving the SPI bus. + We can safely assume its unlikely MMC & telephony HW will be on the same SPI bus, but possible SPI flash and MMC on the same line. So maybe need to feed PF2 into CPLD to allow tri-stating of CPLD output. Or PF5 (MMC select). [X] Make sure PF5 pulled H by default. This will make sure MMC won't drive the bus during serial boot. [X] Make sure at power up nCSx not asserted + this is not a big issue as BBSDO is isolated from SDO via CPLD, which has OE logic on SPIENABLE. However sensible precaution. [X] make sure nCSA and nCSB are pulled high at power up + nCSA is gated to provide nCSx, so as long as this is H we are OK + OK added pullups to nCSA and nCSB [X] Remove MMSDO net + After review by Dimitar, I realsied U3A and U3 were connected to different SDO nets. This would complicate boot. + So I removed MMCSDO net - now SDO connected to two pins of CPLD to simplify routing. U3A and U3 connected to SDO. SDO pin on CPLD stays disabled unless nCSA asserted. So SDO pin on CPLD only asserted to when modules have SPI bus. [X] TDM serial directions OK to modules + changed series terms on PCLK to 10 ohms, 100 seemed too big + made DT0PRI (net DRX) 10 as a precaution, long net [X] CPLD compiles + looks quite tight, consider 2nd CPLD or larger CPLD + fit in OK, I removed a lot of bf1 logic as IP04 doesnt have NOR flash decoding is much simpler [X] compare ip04 to bf1 v2 schematic + look for any pull ups that might be missing on ip04 + pullups on ARDY and BR, SDO, and SPIFLASH all present + don't need PF13 as we don't use it for address decoding on IP04 [X] M25P20 256k x 8 serial flash pin out [X] Check SO-8 solder mask is OK + looks good when viewed on gerbv [ ] visully inspect gerbers for anything strange [X] Final check all TNV-SELV clearances + min of 3.6mm is set by EMI caps [ ] Manufacture [ ] re-align BOM spreadsheet and sch + I cant remember if U9/U10 were on spreadsheet + component have changed values + make sure manufacture information is correct [ ] EMI ideas [ ] modulate SPI clock to reduce EMI + done by default with bit bashed SPI + SPI hw clock could also be tweaked - good idea [ ] can bfin CPU clock change every ms or so? + we should look into this + could really help EMI [ ] can we module the TDM clock? + or does it need to be synchronous with 2.048MHz [ ] Software [ ] ST MP25P20 256k serial flash support [ ] establish u-boot support [ ] Work out how to program it with an Igloo [ ] modify u-boot for AMS0 selected NAND flash [ ] modify u-boot for AMS1 selected Ethernet + PF13 bank selection not needed now [ ] modify uClinux for AMS0 selected NAND flash [ ] modify uClinux for AMS1 selected Ethernet + PF13 bank selection not needed now [ ] Modify drivers for interrupt driven rather than polling operation [ ] Modify drivers for easy switching between interrupt driven and polling, bit-bashed and regular SPI [ ] Oslec optimisation [ ] complete 32-16 bit port [ ] use some blackfin assembler [ ] dot product for filtering [ ] LMS update [ ] u-boot [ ] resaerch changes [ ] new board directory [ ] board/bf1/spi.c + check commands same for M25P20 Long Term --------- [ ] Watchdog in bfin + see if any HW required. [ ] Can we find a smaller Flash part, like 32MB + must be common parts - talk to DM9000 guys [ ] some day need to make sure all PCB values match those on sch + schematic is the reference, use this for BOM, loading etc [ ] research cascading JTAGs + connect TDO to TDI + protoype if we think possible, demo bf JTAG and Xilinx prog + Eko has used an Igloo to program the CPLD, not sure about cascading [X] get rid of old numbered NC parts,m replace with gschem standard NC [ ] consolidate different footprints of the same part like d603 and bf_0603 [ ] consistent naming styles like 0.1uF v 100nF [ ] replace embedded symbols in sch, these seen to have funny refdes's embedded within. Use symbol library [ ] Knock up a spreadsheet based on lowest cost bfin system + BF531, 16M, small flash + RS232 aand Ethernet + don't load 4fx side of PCB + target sub $100 [ ] Check out lower cost SDRAM alternatives + e.g. ELPIDA SDRAM (EDS2516AFTA) 32M x 16 $3.20 in Qty 1000! Much cheaper than Micron Rev 642 PCB Bugs/Comments ------------------------- Assembly Notes -------------- [ ] C117 & C120 transposed [ ] U3A pin1 is on side with 45 deg bevel Major ----- [X] C117 and C120 labels transposed + this caused an explosion on the prototype as the voltage ratings are different! + just load both as 25V 10uF for now [X] fixed in schem/PCB [X] VDDRTC NC + connect to 3V3 otherwise RTC wont start, which means u-boot won't start [X] fixed in schem/PCB Minor ----- [ ] U7 designator missing from near CPLD [ ] C42 refdes too far away from cap [ ] Does R5 need to be 4k7 + can it be 10k? [ ] Can R121 and R120 be 10k? + save loading another reel [ ] consider changing C164 C166 foot prints + caps I mounted were smaller in pad spacing + poss use SM [ ] Vias used as test points + e.g. earths, databus pads under U6 + dont have enough bare copper to solder to + mask covers most of pad + use proper test point footprint + something will large solderable area [ ] Q1 32kHz Xtal package + this has thin leads and can bend easily + change package to something can be soldered down + or consider SM [ ] U2 SDRAM footprint + could be improved, shorter but fatter (wider) pads [ ] silkscreen issues + lines around small 0603 resistors and caps + lines v thin, sometimes dont come out well + also slightly offset + not sure if this is registration problem or foot prints + CPLD outline within pads, could cause probs with some manufacturers + check min slikscreen width [ ] drills holes slightly off centre + slight misalignment on vias, thru hole pads + could be PCB or foot print errors + this has happened to all my designs from gEDA-PCB Bringup Notes ------------- [ ] cp modified ip04_cpld.v back into svn [ ] check in working CPLD jed file