README for IP04 --------------- An open (free as in speech) four port IP-PBX design, derived from the 4fx and BlackfinOne V2. The target assembly cost (including all parts and labour but not testing) is $200 in Qty 50, and $100 in Qty 5-10k. Pronunciation -------------- IP04 "Eye-Pee-Four", a four port IP-PBX. Might be followed by IP08, IP32 etc. Specs ----- + 2 layer PCB measuring 200mm by 100mm + BF532 400MHz + 64M SD-RAM running at 133MHz + 32-256M NAND Flash for Asterisk Application, prompt and voicemail storage + 4 FXS/FXO modules (fxsmod and fxomod designs) + Optional stackable with 4fx cards to get 8 or even 12 analog ports + Optional MMC card for removable flash storage + Approximate assembly cost (including parts and labour) US$200 in Qty 50 + Includes case but not 12-20V power supply + Software echo cancellation using OSLEC (David's Open line echo canceller) + Astfin Blackfin uClinux-Asterisk 1.4 software build Options ------- + DNL (Do Not Load) 4fx side of board to get a low cost Blackfin starter kit. + Load 16M or 32M RAM or BF531 for lower cost. Asterisk will probably run in 32M. You can run uClinux and do lots of useful things in 16M. + DNL RS232 hardware to save a few $ if you don't need console access. + 0-4 FXO/FXS port options, e.g. some people might only want 1 or two ports. Design Philosophy ----------------- 1/ Lowest possible price for a 4 analog port IP-PBX, hence: + Removed 2nd Ethernet port, USB and buffers from BlackfinOne V2 + Combined BlackfinOne V2 core with 4fx PCB, one PCB is cheaper than 2 + NAND Flash rather than NOR 2/ Easy for anyone with x86 Asterisk experience to use - you don't need to an embedded system expert or climb a huge learning curve: + You will get dial tone when power is applied + Persistent config files (e.g. /etc/asterisk/*.conf in flash) + Single 'make' build system (thanks Astfin team) + Asterisk 1.4 GUI (thanks Digium and Asterisk contributors) 3/ The entire hardware design is open and will remain that way Files ----- *.sch Schematics in gEDA gschem format ip04.pcb PCB design in gEDA PCB format ip04_bom.xls Costed BOM and analysis of build costs in Qty TODO List of tasks we need to work through Links ----- Free Telephony Project http://www.rowetel.com/ucasterisk BlackfinOne http://blackfin.uclinux.org/gf/project/bf1/ 4fx analog hardware http://www.rowetel.com/ucasterisk/4fx.html HOWTO ----- 1/ To perform a schematic DRC: $ gnetlist -g drc2 -o - ip04_cpu.sch ip04_mem.sch ip04_4fx.sch 2/ To generate the netlist: $ gnetlist -g PCB -o ip04.net ip04_cpu.sch ip04_mem.sch ip04_4fx.sch TIPS ---- 3/ Finding duplicate elements in a PCB file: $ grep -E "Element.*R12\"" ip04.pcb DESIGN NOTES ============ 1/ Two SPI Busses ----------------- Note that the Blackfin SPI port signals SCLK/SDO/SPI are fed to the CPLD, and that there is a second (bit bashed) SPI bus BBSCL/BBSDO/BBSDI. Having two busses is the solution to simultaneous MMC card and telephony hardware access. The BB SPI bus is generated in software via the PF pins. This is slower than hardware SPI. Using interrupts rather thna polling to monitor status of the telephony hardware will overcome this. Alternatively, we can join the two buses inside the CPLD in situations where the MMC card is not required. Note that this scheme means the MMC card cannot be used on stacked 4fx daughter cards, as only the BB SPI port is available on J5. Bit Bashing (curiously) will also reduce EMI compared to hardware SPI, as the clock will be more random, spreading spectal energy away from one frequency. An Analog Devices App note suggested that it is possible to use the high speed serial port to interface with SPI devices. Therefore the 2nd serial ports lines have been routed to the CPLD to allow for this options. This is an excellent solution as the serial port is fast, low overhead, and we have working drivers for it already. In this case, nCSA and nCSB would be asserted to control the LEDs and chip select of the module, as per the regular SPI HW. These would be driven by the serial port, asserting the PF pins in software before sending the serial words. Some analysis has been performed to make sure the CPLD SDO output only drives the SDO net when nCSA is asserted. This prevents contention at boot time, when the SPI flash must drive the net. See TODO and ip04_cpld.v for more information. 2/ CAD Tools ------------ + gEDA gschem 20060906 + gEDA PCB 20070208p1, 10 mil tracks for most signals, 8mil when tight, 5mil grid 3/ High Speed Design on Two Layer Boards ---------------------------------------- The original BlackfinOne v1 designers (Ivan and DImiatr) have pioneered the techniques of high speed digital design on two layers boards, which is generally regarded as impossible! Conventional design says you need multilayer boards with cround and power planes to maintain signal integrity (ie to get nice clean signals from point A to B so that your circuit will run). Until this project I would not have beleived a 133MHz external bus could run on a two layer board. It shouldn't work. But it does! A two layer board makes PCB production much cheaper to hackers. + The SDRAM is located directly behind the Blackfin, this gives the shortest possible net lengths, and couldnt be improved on even with a multi-layer PCB. + where possible keep all track son top layer, leaving as much room as possible for unbroken ground plane. + When you need to route over the bottomn layer do it quickly and return to the top layer ASAP, minimising breaks in the ground plane. Never route long tracks entirely on the bottom layer. + Place decoupling caps as close as possible to GND/VCC pins. For high speed operation these caps are the power supplies of the circuit - they supply the short bursts of current required to power the chip. The power supply tracks are merely used to recharge these caps and are of lower importance. + Always think about where the currents flow. Current flows in a loop, out of an output pin, along the trace to a input pin, then back through the ground pins along the ground plane. Current is lazy, it will take the shortest path through the ground plane, as this is the path of least resistance. This current loop will form an inductor, the smaller the loop area the smaller the inductor. Minimise the loop area. This minimises inductance, which minimises the impedance (resistance) to the current flow and minimises EMI (small loops are poor antennas, they do not radiate effectively). + In several places tracks and planes have been placed to help minimise the loop area, for example a ground track has been placed parallel to the PCLK net along the top of J1A to J4A. Where the ground plane has been interrupted top layer tracks/plane have been used to stitch it back together. This provides a shorter path for the return currents, lowering loop area and impedance, improving signal integrity, and lowering radiated EMI. + The high speed bus area is about 40mm by 40mm. The maximum loop will therefore be about 80mm (40mm output to input, 40mm back thorugh GND nets/plane). A 80mm loop will be an effective radiator at f = 300E6/0.08 = 3.75GHz, which is well above where EMI measurements will occur (FCC-15 measurments re limited to 1500 MHz for a 400MHz max clock). However antennas also radiate when they are 1/4 and 1/2 of wavelength. For example a 1/4 wavelength 80mm antenna may radiate 937MHz well. This is the 7th harmonic of 133MHz so some energy may be present to excite the antenna at that frequency. Test & Expansion Points ----------------------- These are just vias I have labelled to assist in testing and possible future expansion. They aren't on the schematic. 1/ There are 3 (unconnected) EARTH points (just vias really). These are provided as alternate eartching points, might be handy for combatting EMC. The mounting holes are connected to digital GND. 2/ There are also some testpoints (vias) near the BF532 for Vrtc (real time clock battery power) and CLKOUT. 3/ The 4 unused CPLD IO pins are broken out to vias to make them easy to solder to. 4/ A few of the external memory bus nets have been broken out, for example D[0-7], A2, AWE, ARD, and AMS2. This will allow some basic memory mapping of 8-bit peripherals. If you use these be sure to buffer very close to the IP04 PCB, as these points access the raw, unbuffered high speed data bus running at 133MHz. Excessive loading will kill the IP04 operation. It probably easier to use SPI or the high speed serial ports however.